[CodeGen][NFC] Regenerate load-combine test with update_llc_test.

To prepare for D27861.

1 files changed, 234 insertions, 175 deletions

diff --git a/llvm/test/CodeGen/ARM/load-combine.ll b/llvm/test/CodeGen/ARM/load-combine.ll
index 4206aad1d9e..03f4771c5a7 100644
--- a/llvm/test/CodeGen/ARM/load-combine.ll
+++ b/llvm/test/CodeGen/ARM/load-combine.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=arm-unknown | FileCheck %s
 ; RUN: llc < %s -mtriple=armv6-unknown | FileCheck %s --check-prefix=CHECK-ARMv6
 
@@ -5,20 +6,27 @@
 ; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
 define i32 @load_i32_by_i8_unaligned(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_unaligned:
-; CHECK: ldrb{{.*}}r0
-; CHECK: ldrb{{.*}}r0
-; CHECK: ldrb{{.*}}r0
-; CHECK: ldrb{{.*}}r0
-; CHECK: orr
-; CHECK: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldrb r2, [r0, #1]
+; CHECK-NEXT:    ldrb r1, [r0]
+; CHECK-NEXT:    ldrb r3, [r0, #2]
+; CHECK-NEXT:    ldrb r0, [r0, #3]
+; CHECK-NEXT:    orr r1, r1, r2, lsl #8
+; CHECK-NEXT:    orr r1, r1, r3, lsl #16
+; CHECK-NEXT:    orr r0, r1, r0, lsl #24
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_unaligned:
-; CHECK-ARMv6: ldrb{{.*}}r0
-; CHECK-ARMv6: ldrb{{.*}}r0
-; CHECK-ARMv6: ldrb{{.*}}r0
-; CHECK-ARMv6: ldrb{{.*}}r0
-; CHECK-ARMv6: orr
-; CHECK-ARMv6: bx lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldrb r2, [r0, #1]
+; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
+; CHECK-ARMv6-NEXT:    ldrb r3, [r0, #2]
+; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #3]
+; CHECK-ARMv6-NEXT:    orr r1, r1, r2, lsl #8
+; CHECK-ARMv6-NEXT:    orr r1, r1, r3, lsl #16
+; CHECK-ARMv6-NEXT:    orr r0, r1, r0, lsl #24
+; CHECK-ARMv6-NEXT:    bx lr
+
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp2 = load i8, i8* %tmp1, align 1
@@ -45,12 +53,15 @@ define i32 @load_i32_by_i8_unaligned(i32* %arg) {
 ; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
 define i32 @load_i32_by_i8_aligned(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_aligned:
-; CHECK: ldr  r0, [r0]
-; CHECK-NEXT: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_aligned:
-; CHECK-ARMv6: ldr  r0, [r0]
-; CHECK-ARMv6-NEXT: bx lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldr r0, [r0]
+; CHECK-ARMv6-NEXT:    bx lr
+
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp2 = load i8, i8* %tmp1, align 4
@@ -78,18 +89,23 @@ define i32 @load_i32_by_i8_aligned(i32* %arg) {
 define i32 @load_i32_by_i8_bswap(i32* %arg) {
 ; BSWAP is not supported by 32 bit target
 ; CHECK-LABEL: load_i32_by_i8_bswap:
-; CHECK: ldr r0, [r0]
-; CHECK: and
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    mov r1, #65280
+; CHECK-NEXT:    mov r2, #16711680
+; CHECK-NEXT:    and r1, r1, r0, lsr #8
+; CHECK-NEXT:    and r2, r2, r0, lsl #8
+; CHECK-NEXT:    orr r1, r1, r0, lsr #24
+; CHECK-NEXT:    orr r0, r2, r0, lsl #24
+; CHECK-NEXT:    orr r0, r0, r1
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
-; CHECK-ARMv6: ldr  r0, [r0]
-; CHECK-ARMv6-NEXT: rev  r0, r0
-; CHECK-ARMv6-NEXT: bx lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldr r0, [r0]
+; CHECK-ARMv6-NEXT:    rev r0, r0
+; CHECK-ARMv6-NEXT:    bx lr
+
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = load i8, i8* %tmp, align 4
   %tmp2 = zext i8 %tmp1 to i32
@@ -115,14 +131,17 @@ define i32 @load_i32_by_i8_bswap(i32* %arg) {
 ; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
 define i64 @load_i64_by_i8(i64* %arg) {
 ; CHECK-LABEL: load_i64_by_i8:
-; CHECK: ldr r2, [r0]
-; CHECK-NEXT: ldr r1, [r0, #4]
-; CHECK-NEXT: mov r0, r2
-; CHECK-NEXT: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r2, [r0]
+; CHECK-NEXT:    ldr r1, [r0, #4]
+; CHECK-NEXT:    mov r0, r2
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i64_by_i8:
-; CHECK-ARMv6: ldrd  r0, r1, [r0]
-; CHECK-ARMv6: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldrd r0, r1, [r0]
+; CHECK-ARMv6-NEXT:    bx lr
+
   %tmp = bitcast i64* %arg to i8*
   %tmp1 = load i8, i8* %tmp, align 8
   %tmp2 = zext i8 %tmp1 to i64
@@ -168,25 +187,32 @@ define i64 @load_i64_by_i8(i64* %arg) {
 ; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
 define i64 @load_i64_by_i8_bswap(i64* %arg) {
 ; CHECK-LABEL: load_i64_by_i8_bswap:
-; CHECK: ldr{{.*}}r0
-; CHECK: ldr{{.*}}r0
-; CHECK: and
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: and
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK-NEXT: orr
-; CHECK: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    push {r11, lr}
+; CHECK-NEXT:    ldr r1, [r0]
+; CHECK-NEXT:    mov r12, #65280
+; CHECK-NEXT:    ldr r0, [r0, #4]
+; CHECK-NEXT:    mov lr, #16711680
+; CHECK-NEXT:    and r3, r12, r0, lsr #8
+; CHECK-NEXT:    and r2, lr, r0, lsl #8
+; CHECK-NEXT:    orr r3, r3, r0, lsr #24
+; CHECK-NEXT:    orr r0, r2, r0, lsl #24
+; CHECK-NEXT:    and r2, r12, r1, lsr #8
+; CHECK-NEXT:    orr r0, r0, r3
+; CHECK-NEXT:    and r3, lr, r1, lsl #8
+; CHECK-NEXT:    orr r2, r2, r1, lsr #24
+; CHECK-NEXT:    orr r1, r3, r1, lsl #24
+; CHECK-NEXT:    orr r1, r1, r2
+; CHECK-NEXT:    pop {r11, lr}
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
-; CHECK-ARMv6: ldrd  r2, r3, [r0]
-; CHECK-ARMv6: rev r0, r3
-; CHECK-ARMv6: rev r1, r2
-; CHECK-ARMv6: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldrd r2, r3, [r0]
+; CHECK-ARMv6-NEXT:    rev r0, r3
+; CHECK-ARMv6-NEXT:    rev r1, r2
+; CHECK-ARMv6-NEXT:    bx lr
+
   %tmp = bitcast i64* %arg to i8*
   %tmp1 = load i8, i8* %tmp, align 8
   %tmp2 = zext i8 %tmp1 to i64
@@ -232,12 +258,15 @@ define i64 @load_i64_by_i8_bswap(i64* %arg) {
 ; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24)
 define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
-; CHECK: ldr r0, [r0, #1]
-; CHECK-NEXT: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r0, [r0, #1]
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset:
-; CHECK-ARMv6: ldr r0, [r0, #1]
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldr r0, [r0, #1]
+; CHECK-ARMv6-NEXT:    bx lr
+
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
@@ -265,12 +294,15 @@ define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
 ; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24)
 define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_neg_offset:
-; CHECK: ldr r0, [r0, #-4]
-; CHECK-NEXT: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r0, [r0, #-4]
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset:
-; CHECK-ARMv6: ldr r0, [r0, #-4]
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldr r0, [r0, #-4]
+; CHECK-ARMv6-NEXT:    bx lr
+
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -4
@@ -298,20 +330,23 @@ define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
 ; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24)
 define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
-; CHECK: ldr r0, [r0, #1]
-; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
-; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
-; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
-; CHECK-NEXT: orr r0, r0, r1
-; CHECK-NEXT: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r0, [r0, #1]
+; CHECK-NEXT:    mov r1, #65280
+; CHECK-NEXT:    mov r2, #16711680
+; CHECK-NEXT:    and r1, r1, r0, lsr #8
+; CHECK-NEXT:    and r2, r2, r0, lsl #8
+; CHECK-NEXT:    orr r1, r1, r0, lsr #24
+; CHECK-NEXT:    orr r0, r2, r0, lsl #24
+; CHECK-NEXT:    orr r0, r0, r1
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap:
-; CHECK-ARMv6: ldr r0, [r0, #1]
-; CHECK-ARMv6-NEXT: rev r0, r0
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldr r0, [r0, #1]
+; CHECK-ARMv6-NEXT:    rev r0, r0
+; CHECK-ARMv6-NEXT:    bx lr
+
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 4
@@ -339,20 +374,23 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
 ; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24)
 define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
-; CHECK: ldr r0, [r0, #-4]
-; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
-; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
-; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
-; CHECK-NEXT: orr r0, r0, r1
-; CHECK-NEXT: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r0, [r0, #-4]
+; CHECK-NEXT:    mov r1, #65280
+; CHECK-NEXT:    mov r2, #16711680
+; CHECK-NEXT:    and r1, r1, r0, lsr #8
+; CHECK-NEXT:    and r2, r2, r0, lsl #8
+; CHECK-NEXT:    orr r1, r1, r0, lsr #24
+; CHECK-NEXT:    orr r0, r2, r0, lsl #24
+; CHECK-NEXT:    orr r0, r0, r1
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap:
-; CHECK-ARMv6: ldr r0, [r0, #-4]
-; CHECK-ARMv6-NEXT: rev r0, r0
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldr r0, [r0, #-4]
+; CHECK-ARMv6-NEXT:    rev r0, r0
+; CHECK-ARMv6-NEXT:    bx lr
+
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 -1
@@ -382,20 +420,23 @@ declare i16 @llvm.bswap.i16(i16)
 ; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16)
 define i32 @load_i32_by_bswap_i16(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_bswap_i16:
-; CHECK: ldr  r0, [r0]
-; CHECK-NEXT: mov r1, #65280
-; CHECK-NEXT: mov r2, #16711680
-; CHECK-NEXT: and r1, r1, r0, lsr #8
-; CHECK-NEXT: and r2, r2, r0, lsl #8
-; CHECK-NEXT: orr r1, r1, r0, lsr #24
-; CHECK-NEXT: orr r0, r2, r0, lsl #24
-; CHECK-NEXT: orr r0, r0, r1
-; CHECK-NEXT: mov pc, lr
-
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    mov r1, #65280
+; CHECK-NEXT:    mov r2, #16711680
+; CHECK-NEXT:    and r1, r1, r0, lsr #8
+; CHECK-NEXT:    and r2, r2, r0, lsl #8
+; CHECK-NEXT:    orr r1, r1, r0, lsr #24
+; CHECK-NEXT:    orr r0, r2, r0, lsl #24
+; CHECK-NEXT:    orr r0, r0, r1
+; CHECK-NEXT:    mov pc, lr
+;
 ; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
-; CHECK-ARMv6: ldr r0, [r0]
-; CHECK-ARMv6-NEXT: rev r0, r0
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldr r0, [r0]
+; CHECK-ARMv6-NEXT:    rev r0, r0
+; CHECK-ARMv6-NEXT:    bx lr
+
 
   %tmp = bitcast i32* %arg to i16*
   %tmp1 = load i16, i16* %tmp, align 4
@@ -414,12 +455,14 @@ define i32 @load_i32_by_bswap_i16(i32* %arg) {
 ; (i32) p[0] | (sext(p[1] << 16) to i32)
 define i32 @load_i32_by_sext_i16(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_sext_i16:
-; CHECK: ldr  r0, [r0]
-; CHECK-NEXT: mov pc, lr
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldr r0, [r0]
+; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_sext_i16:
-; CHECK-ARMv6: ldr  r0, [r0]
-; CHECK-ARMv6-NEXT: bx lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldr r0, [r0]
+; CHECK-ARMv6-NEXT:    bx lr
   %tmp = bitcast i32* %arg to i16*
   %tmp1 = load i16, i16* %tmp, align 4
   %tmp2 = zext i16 %tmp1 to i32
@@ -436,14 +479,16 @@ define i32 @load_i32_by_sext_i16(i32* %arg) {
 ; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24)
 define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index:
-; CHECK: add r0, r0, r1
-; CHECK-NEXT: ldr r0, [r0, #12]
-; CHECK-NEXT: mov pc, lr
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    add r0, r0, r1
+; CHECK-NEXT:    ldr r0, [r0, #12]
+; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index:
-; CHECK-ARMv6: add r0, r0, r1
-; CHECK-ARMv6-NEXT: ldr r0, [r0, #12]
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    add r0, r0, r1
+; CHECK-ARMv6-NEXT:    ldr r0, [r0, #12]
+; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = add nuw nsw i32 %i, 3
   %tmp2 = add nuw nsw i32 %i, 2
@@ -479,14 +524,16 @@ define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
 ; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
 define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
-; CHECK: add r0, r1, r0
-; CHECK-NEXT: ldr r0, [r0, #13]
-; CHECK-NEXT: mov pc, lr
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    add r0, r1, r0
+; CHECK-NEXT:    ldr r0, [r0, #13]
+; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:
-; CHECK-ARMv6: add r0, r1, r0
-; CHECK-ARMv6-NEXT: ldr r0, [r0, #13]
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    add r0, r1, r0
+; CHECK-ARMv6-NEXT:    ldr r0, [r0, #13]
+; CHECK-ARMv6-NEXT:    bx lr
   %tmp = add nuw nsw i32 %i, 4
   %tmp2 = add nuw nsw i32 %i, 3
   %tmp3 = add nuw nsw i32 %i, 2
@@ -521,16 +568,18 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
 ; (i32) p[0] | ((i32) p[1] << 8)
 define i32 @zext_load_i32_by_i8(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8:
-; CHECK: ldrb  r1, [r0]
-; CHECK-NEXT: ldrb  r0, [r0, #1]
-; CHECK-NEXT: orr r0, r1, r0, lsl #8
-; CHECK-NEXT: mov pc, lr
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldrb r1, [r0]
+; CHECK-NEXT:    ldrb r0, [r0, #1]
+; CHECK-NEXT:    orr r0, r1, r0, lsl #8
+; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8:
-; CHECK-ARMv6: ldrb  r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb  r0, [r0, #1]
-; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #8
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
+; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
+; CHECK-ARMv6-NEXT:    orr r0, r1, r0, lsl #8
+; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
@@ -548,18 +597,20 @@ define i32 @zext_load_i32_by_i8(i32* %arg) {
 ; ((i32) p[0] << 8) | ((i32) p[1] << 16)
 define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_shl_8:
-; CHECK: ldrb  r1, [r0]
-; CHECK-NEXT: ldrb  r0, [r0, #1]
-; CHECK-NEXT: lsl r0, r0, #16
-; CHECK-NEXT: orr r0, r0, r1, lsl #8
-; CHECK-NEXT: mov pc, lr
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldrb r1, [r0]
+; CHECK-NEXT:    ldrb r0, [r0, #1]
+; CHECK-NEXT:    lsl r0, r0, #16
+; CHECK-NEXT:    orr r0, r0, r1, lsl #8
+; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_shl_8:
-; CHECK-ARMv6: ldrb  r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb  r0, [r0, #1]
-; CHECK-ARMv6-NEXT: lsl r0, r0, #16
-; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #8
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
+; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
+; CHECK-ARMv6-NEXT:    lsl r0, r0, #16
+; CHECK-ARMv6-NEXT:    orr r0, r0, r1, lsl #8
+; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
@@ -578,18 +629,20 @@ define i32 @zext_load_i32_by_i8_shl_8(i32* %arg) {
 ; ((i32) p[0] << 16) | ((i32) p[1] << 24)
 define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_shl_16:
-; CHECK: ldrb  r1, [r0]
-; CHECK-NEXT: ldrb  r0, [r0, #1]
-; CHECK-NEXT: lsl r0, r0, #24
-; CHECK-NEXT: orr r0, r0, r1, lsl #16
-; CHECK-NEXT: mov pc, lr
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldrb r1, [r0]
+; CHECK-NEXT:    ldrb r0, [r0, #1]
+; CHECK-NEXT:    lsl r0, r0, #24
+; CHECK-NEXT:    orr r0, r0, r1, lsl #16
+; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_shl_16:
-; CHECK-ARMv6: ldrb  r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb  r0, [r0, #1]
-; CHECK-ARMv6-NEXT: lsl r0, r0, #24
-; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #16
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
+; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
+; CHECK-ARMv6-NEXT:    lsl r0, r0, #24
+; CHECK-ARMv6-NEXT:    orr r0, r0, r1, lsl #16
+; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
@@ -608,16 +661,18 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
 ; (i32) p[1] | ((i32) p[0] << 8)
 define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_bswap:
-; CHECK: ldrb  r1, [r0]
-; CHECK-NEXT: ldrb  r0, [r0, #1]
-; CHECK-NEXT: orr r0, r0, r1, lsl #8
-; CHECK-NEXT: mov pc, lr
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldrb r1, [r0]
+; CHECK-NEXT:    ldrb r0, [r0, #1]
+; CHECK-NEXT:    orr r0, r0, r1, lsl #8
+; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap:
-; CHECK-ARMv6: ldrb  r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb  r0, [r0, #1]
-; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #8
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
+; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
+; CHECK-ARMv6-NEXT:    orr r0, r0, r1, lsl #8
+; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
@@ -635,18 +690,20 @@ define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
 ; ((i32) p[1] << 8) | ((i32) p[0] << 16)
 define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_8:
-; CHECK: ldrb  r1, [r0]
-; CHECK-NEXT: ldrb  r0, [r0, #1]
-; CHECK-NEXT: lsl r1, r1, #16
-; CHECK-NEXT: orr r0, r1, r0, lsl #8
-; CHECK-NEXT: mov pc, lr
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldrb r1, [r0]
+; CHECK-NEXT:    ldrb r0, [r0, #1]
+; CHECK-NEXT:    lsl r1, r1, #16
+; CHECK-NEXT:    orr r0, r1, r0, lsl #8
+; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap_shl_8:
-; CHECK-ARMv6: ldrb  r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb  r0, [r0, #1]
-; CHECK-ARMv6-NEXT: lsl r1, r1, #16
-; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #8
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
+; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
+; CHECK-ARMv6-NEXT:    lsl r1, r1, #16
+; CHECK-ARMv6-NEXT:    orr r0, r1, r0, lsl #8
+; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
@@ -665,18 +722,20 @@ define i32 @zext_load_i32_by_i8_bswap_shl_8(i32* %arg) {
 ; ((i32) p[1] << 16) | ((i32) p[0] << 24)
 define i32 @zext_load_i32_by_i8_bswap_shl_16(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_bswap_shl_16:
-; CHECK: ldrb  r1, [r0]
-; CHECK-NEXT: ldrb  r0, [r0, #1]
-; CHECK-NEXT: lsl r1, r1, #24
-; CHECK-NEXT: orr r0, r1, r0, lsl #16
-; CHECK-NEXT: mov pc, lr
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    ldrb r1, [r0]
+; CHECK-NEXT:    ldrb r0, [r0, #1]
+; CHECK-NEXT:    lsl r1, r1, #24
+; CHECK-NEXT:    orr r0, r1, r0, lsl #16
+; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap_shl_16:
-; CHECK-ARMv6: ldrb  r1, [r0]
-; CHECK-ARMv6-NEXT: ldrb  r0, [r0, #1]
-; CHECK-ARMv6-NEXT: lsl r1, r1, #24
-; CHECK-ARMv6-NEXT: orr r0, r1, r0, lsl #16
-; CHECK-ARMv6-NEXT: bx  lr
+; CHECK-ARMv6:       @ %bb.0:
+; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
+; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
+; CHECK-ARMv6-NEXT:    lsl r1, r1, #24
+; CHECK-ARMv6-NEXT:    orr r0, r1, r0, lsl #16
+; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1