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| author | Eli Friedman <efriedma@codeaurora.org> | 2018-10-26 19:32:24 +0000 |
|---|---|---|
| committer | Eli Friedman <efriedma@codeaurora.org> | 2018-10-26 19:32:24 +0000 |
| commit | 2ac116291729fa8f9af82f4b7005c0839aff7fa9 (patch) | |
| tree | 08572d466833e355e98615e522ff8b985378ff5b /llvm/test/CodeGen/ARM/intrinsics-overflow.ll | |
| parent | 6822bd79ac43f267613f1615bf60407103e24dba (diff) | |
| download | bcm5719-llvm-2ac116291729fa8f9af82f4b7005c0839aff7fa9.tar.gz bcm5719-llvm-2ac116291729fa8f9af82f4b7005c0839aff7fa9.zip | |
[ARM] Make InstrEmitter mark CPSR defs dead for Thumb1.
The "dead" markings allow existing target-independent optimizations,
like MachineSink, to trigger more frequently. The CPSR defs would have
eventually been marked dead by LiveVariables, so this only affects
optimizations before regalloc.
The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible
with this change: the transform adds a use to an otherwise dead def
of CPSR. This is covered by existing regression tests.
thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the
generated code; I'll fix it in D53452.
Differential Revision: https://reviews.llvm.org/D53453
llvm-svn: 345420
Diffstat (limited to 'llvm/test/CodeGen/ARM/intrinsics-overflow.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/intrinsics-overflow.ll | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll index 835be7e949d..d4c20dfacce 100644 --- a/llvm/test/CodeGen/ARM/intrinsics-overflow.ll +++ b/llvm/test/CodeGen/ARM/intrinsics-overflow.ll @@ -38,14 +38,9 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 { ; ARM: movvc r[[R0]], #0 ; ARM: mov pc, lr - ; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]] - ; THUMBV6: adds r[[R3:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] - ; THUMBV6: movs r[[R0]], #0 - ; THUMBV6: movs r[[R1]], #1 - ; THUMBV6: cmp r[[R3]], r[[R2]] - ; THUMBV6: bvc .L[[LABEL:.*]] - ; THUMBV6: mov r[[R0]], r[[R1]] - ; THUMBV6: .L[[LABEL]]: + ; THUMBV6: adds r1, r0, r1 + ; THUMBV6: cmp r1, r0 + ; THUMBV6: bvc .LBB1_2 ; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]] ; THUMBV7: mov.w r[[R0:[0-9]+]], #1 @@ -94,12 +89,8 @@ define i32 @ssub_overflow(i32 %a, i32 %b) #0 { ; ARM: cmp r[[R0]], r[[R1]] ; ARM: movvc r[[R2]], #0 - ; THUMBV6: movs r[[R0]], #0 - ; THUMBV6: movs r[[R3:[0-9]+]], #1 - ; THUMBV6: cmp r[[R2]], r[[R1:[0-9]+]] - ; THUMBV6: bvc .L[[LABEL:.*]] - ; THUMBV6: mov r[[R0]], r[[R3]] - ; THUMBV6: .L[[LABEL]]: + ; THUMBV6: cmp r0, r1 + ; THUMBV6: bvc .LBB3_2 ; THUMBV7: movs r[[R2:[0-9]+]], #1 ; THUMBV7: cmp r[[R0:[0-9]+]], r[[R1:[0-9]+]] |
