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author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
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committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/ARM/interrupt-attr.ll | |
parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/ARM/interrupt-attr.ll')
-rw-r--r-- | llvm/test/CodeGen/ARM/interrupt-attr.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/interrupt-attr.ll b/llvm/test/CodeGen/ARM/interrupt-attr.ll index c6da09d156b..95ada085b0d 100644 --- a/llvm/test/CodeGen/ARM/interrupt-attr.ll +++ b/llvm/test/CodeGen/ARM/interrupt-attr.ll @@ -65,7 +65,7 @@ define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" { ; CHECK-A-THUMB-LABEL: fiq_fn: ; CHECK-M-LABEL: fiq_fn: - %val = load volatile [16 x i32]* @bigvar + %val = load volatile [16 x i32], [16 x i32]* @bigvar store volatile [16 x i32] %val, [16 x i32]* @bigvar ret void } @@ -81,7 +81,7 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" { ; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} ; CHECK-A: subs pc, lr, #0 - %val = load volatile [16 x i32]* @bigvar + %val = load volatile [16 x i32], [16 x i32]* @bigvar store volatile [16 x i32] %val, [16 x i32]* @bigvar ret void } @@ -126,8 +126,8 @@ define arm_aapcscc void @floating_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-A-NOT: vstr ; CHECK-A-NOT: vstm ; CHECK-A: vadd.f64 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} - %lhs = load volatile double* @var - %rhs = load volatile double* @var + %lhs = load volatile double, double* @var + %rhs = load volatile double, double* @var %sum = fadd double %lhs, %rhs store double %sum, double* @var ret void |