diff options
| author | Joerg Sonnenberger <joerg@bec.de> | 2014-05-06 20:43:01 +0000 |
|---|---|---|
| committer | Joerg Sonnenberger <joerg@bec.de> | 2014-05-06 20:43:01 +0000 |
| commit | 818e72515891d6621567988cd6c1069189e87598 (patch) | |
| tree | e5044a504b93abf6c59b38ac0defdd375afc4300 /llvm/test/CodeGen/ARM/interrupt-attr.ll | |
| parent | bdc969839aa55aec67860165087e1376a89edba2 (diff) | |
| download | bcm5719-llvm-818e72515891d6621567988cd6c1069189e87598.tar.gz bcm5719-llvm-818e72515891d6621567988cd6c1069189e87598.zip | |
If a function needs a frame pointer, but r11 (aka fp) has not been used,
remove it from the list of unspilled registers. Otherwise the following
attempt to keep the stack aligned by picking an extra GPR register to
spill will not work as it picks up r11.
llvm-svn: 208129
Diffstat (limited to 'llvm/test/CodeGen/ARM/interrupt-attr.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/interrupt-attr.ll | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/llvm/test/CodeGen/ARM/interrupt-attr.ll b/llvm/test/CodeGen/ARM/interrupt-attr.ll index 9b7b41ba7ec..c5be6674da1 100644 --- a/llvm/test/CodeGen/ARM/interrupt-attr.ll +++ b/llvm/test/CodeGen/ARM/interrupt-attr.ll @@ -12,13 +12,13 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; Also need special function return setting pc and CPSR simultaneously. ; CHECK-A-LABEL: irq_fn: -; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr} -; CHECK-A: add r11, sp, #16 -; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} +; CHECK-A: add r11, sp, #20 +; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; CHECK-A: bl bar -; CHECK-A: sub sp, r11, #16 -; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr} +; CHECK-A: sub sp, r11, #20 +; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: subs pc, lr, #4 ; CHECK-A-THUMB-LABEL: irq_fn: @@ -35,15 +35,15 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to ; appropriate sentinel so no special return needed). ; CHECK-M-LABEL: irq_fn: -; CHECK-M: push {r4, r7, lr} -; CHECK-M: add r7, sp, #4 +; CHECK-M: push {r4, r6, r7, lr} +; CHECK-M: add r7, sp, #8 ; CHECK-M: mov r4, sp ; CHECK-M: bic r4, r4, #7 ; CHECK-M: mov sp, r4 ; CHECK-M: blx _bar -; CHECK-M: subs r4, r7, #4 +; CHECK-M: sub.w r4, r7, #8 ; CHECK-M: mov sp, r4 -; CHECK-M: pop {r4, r7, pc} +; CHECK-M: pop {r4, r6, r7, pc} call arm_aapcscc void @bar() ret void @@ -88,13 +88,13 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" { define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" { ; CHECK-A-LABEL: undef_fn: -; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr} -; CHECK-A: add r11, sp, #16 -; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} +; CHECK-A: add r11, sp, #20 +; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; [...] -; CHECK-A: sub sp, r11, #16 -; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr} +; CHECK-A: sub sp, r11, #20 +; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: subs pc, lr, #0 call void @bar() @@ -103,13 +103,13 @@ define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" { define arm_aapcscc void @abort_fn() alignstack(8) "interrupt"="ABORT" { ; CHECK-A-LABEL: abort_fn: -; CHECK-A: push {r0, r1, r2, r3, r11, r12, lr} -; CHECK-A: add r11, sp, #16 -; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} +; CHECK-A: add r11, sp, #20 +; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} ; CHECK-A: bic sp, sp, #7 ; [...] -; CHECK-A: sub sp, r11, #16 -; CHECK-A: pop {r0, r1, r2, r3, r11, r12, lr} +; CHECK-A: sub sp, r11, #20 +; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: subs pc, lr, #4 call void @bar() |
