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| author | Simon Tatham <simon.tatham@arm.com> | 2019-06-25 16:49:32 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2019-06-25 16:49:32 +0000 |
| commit | e8de8ba6a637c60d53db2433c0962c3fdbbdbf5c (patch) | |
| tree | b9aa1a7a9ea0881dee88867e12d7271baa5f7f19 /llvm/test/CodeGen/ARM/inlineasm.ll | |
| parent | 88139c143c5f419aa0ed6ba8bb8e70263ffb37cb (diff) | |
| download | bcm5719-llvm-e8de8ba6a637c60d53db2433c0962c3fdbbdbf5c.tar.gz bcm5719-llvm-e8de8ba6a637c60d53db2433c0962c3fdbbdbf5c.zip | |
[ARM] Support inline assembler constraints for MVE.
"To" selects an odd-numbered GPR, and "Te" an even one. There are some
8.1-M instructions that have one too few bits in their register fields
and require registers of particular parity, without necessarily using
a consecutive even/odd pair.
Also, the constraint letter "t" should select an MVE q-register, when
MVE is present. This didn't need any source changes, but some extra
tests have been added.
Reviewers: dmgreen, samparker, SjoerdMeijer
Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D60709
llvm-svn: 364331
Diffstat (limited to 'llvm/test/CodeGen/ARM/inlineasm.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/inlineasm.ll | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/inlineasm.ll b/llvm/test/CodeGen/ARM/inlineasm.ll index 1ed7f6951bb..d7fb442cf5a 100644 --- a/llvm/test/CodeGen/ARM/inlineasm.ll +++ b/llvm/test/CodeGen/ARM/inlineasm.ll @@ -48,3 +48,27 @@ entry: %0 = tail call <4 x float> asm "vadd.f32 $0, $1, $2", "=t,t,t"(<4 x float> %a, <4 x float> %b) ret <4 x float> %0 } + +define i32 @even-GPR-constraint() { +entry: + ; CHECK-LABEL: even-GPR-constraint + ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1 + ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2 + ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3 + ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4 + %0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^Te,=^Te,=^Te,=^Te,0,1,2,3"(i32 0, i32 0, i32 0, i32 0) + %asmresult = extractvalue { i32, i32, i32, i32 } %0, 0 + ret i32 %asmresult +} + +define i32 @odd-GPR-constraint() { +entry: + ; CHECK-LABEL: odd-GPR-constraint + ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #1 + ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #2 + ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #3 + ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #4 + %0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^To,=^To,=^To,=^To,0,1,2,3"(i32 0, i32 0, i32 0, i32 0) + %asmresult = extractvalue { i32, i32, i32, i32 } %0, 0 + ret i32 %asmresult +} |
