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| author | Andrew Trick <atrick@apple.com> | 2011-01-21 05:51:33 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-01-21 05:51:33 +0000 |
| commit | 47ff14b091ee66a4c5f159e7fb8714ca9a66d2f9 (patch) | |
| tree | e1db89bb3f93d14acfd0fbc9f95b8de92ee977fd /llvm/test/CodeGen/ARM/fnmscs.ll | |
| parent | b5e15d1907cd03ea3e1f6e6e675c31be947246a0 (diff) | |
| download | bcm5719-llvm-47ff14b091ee66a4c5f159e7fb8714ca9a66d2f9.tar.gz bcm5719-llvm-47ff14b091ee66a4c5f159e7fb8714ca9a66d2f9.zip | |
Convert -enable-sched-cycles and -enable-sched-hazard to -disable
flags. They are still not enable in this revision.
Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.
Generalized unit tests to work with sched-cycles.
llvm-svn: 123969
Diffstat (limited to 'llvm/test/CodeGen/ARM/fnmscs.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fnmscs.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/fnmscs.ll b/llvm/test/CodeGen/ARM/fnmscs.ll index 5d832537c0f..76c806761f7 100644 --- a/llvm/test/CodeGen/ARM/fnmscs.ll +++ b/llvm/test/CodeGen/ARM/fnmscs.ll @@ -11,7 +11,7 @@ entry: ; NEON: vnmla.f32 ; A8: t1: -; A8: vnmul.f32 s0, s1, s0 +; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}} ; A8: vsub.f32 d0, d0, d1 %0 = fmul float %a, %b %1 = fsub float -0.0, %0 @@ -28,7 +28,7 @@ entry: ; NEON: vnmla.f32 ; A8: t2: -; A8: vnmul.f32 s0, s1, s0 +; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}} ; A8: vsub.f32 d0, d0, d1 %0 = fmul float %a, %b %1 = fmul float -1.0, %0 @@ -45,7 +45,7 @@ entry: ; NEON: vnmla.f64 ; A8: t3: -; A8: vnmul.f64 d16, d16, d17 +; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}} ; A8: vsub.f64 d16, d16, d17 %0 = fmul double %a, %b %1 = fsub double -0.0, %0 @@ -62,7 +62,7 @@ entry: ; NEON: vnmla.f64 ; A8: t4: -; A8: vnmul.f64 d16, d16, d17 +; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}} ; A8: vsub.f64 d16, d16, d17 %0 = fmul double %a, %b %1 = fmul double -1.0, %0 |
