Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.

llvm-svn: 118922

1 files changed, 25 insertions, 14 deletions

diff --git a/llvm/test/CodeGen/ARM/fmscs.ll b/llvm/test/CodeGen/ARM/fmscs.ll
index 7a70543dee6..a182833a7a2 100644
--- a/llvm/test/CodeGen/ARM/fmscs.ll
+++ b/llvm/test/CodeGen/ARM/fmscs.ll
@@ -1,24 +1,35 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
-; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
-; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
 
-define float @test(float %acc, float %a, float %b) {
+define float @t1(float %acc, float %a, float %b) {
 entry:
+; VFP2: t1:
+; VFP2: vnmls.f32
+
+; NEON: t1:
+; NEON: vnmls.f32
+
+; A8: t1:
+; A8: vmul.f32
+; A8: vsub.f32
 	%0 = fmul float %a, %b
         %1 = fsub float %0, %acc
 	ret float %1
 }
 
-; VFP2: test:
-; VFP2: 	vnmls.f32	s2, s1, s0
+define double @t2(double %acc, double %a, double %b) {
+entry:
+; VFP2: t2:
+; VFP2: vnmls.f64
 
-; NFP1: test:
-; NFP1: 	vnmls.f32	s2, s1, s0
-; NFP0: test:
-; NFP0: 	vnmls.f32	s2, s1, s0
+; NEON: t2:
+; NEON: vnmls.f64
 
-; CORTEXA8: test:
-; CORTEXA8: 	vnmls.f32	s2, s1, s0
-; CORTEXA9: test:
-; CORTEXA9: 	vnmls.f32	s2, s1, s0
+; A8: t2:
+; A8: vmul.f64
+; A8: vsub.f64
+	%0 = fmul double %a, %b
+        %1 = fsub double %0, %acc
+	ret double %1
+}