[ARM] Generate vcmp instead of vcmpe

Based on the discussion in
http://lists.llvm.org/pipermail/llvm-dev/2019-October/135574.html, the
conclusion was reached that the ARM backend should produce vcmp instead
of vcmpe instructions by default, i.e. not be producing an Invalid
Operation exception when either arguments in a floating point compare
are quiet NaNs.

In the future, after constrained floating point intrinsics for floating
point compare have been introduced, vcmpe instructions probably should
be produced for those intrinsics - depending on the exact semantics
they'll be defined to have.

This patch logically consists of the following parts:
- Revert http://llvm.org/viewvc/llvm-project?rev=294945&view=rev and
  http://llvm.org/viewvc/llvm-project?rev=294968&view=rev, which
  implemented fine-tuning for when to produce vcmpe (i.e. not do it for
  equality comparisons). The complexity introduced by those patches
  isn't needed anymore if we just always produce vcmp instead. Maybe
  these patches need to be reintroduced again once support is needed to
  map potential LLVM-IR constrained floating point compare intrinsics to
  the ARM instruction set.
- Simply select vcmp, instead of vcmpe, see simple changes in
  lib/Target/ARM/ARMInstrVFP.td
- Adapt lots of tests that tested for vcmpe (instead of vcmp). For all
  of these test, the intent of what is tested for isn't related to
  whether the vcmp should produce an Invalid Operation exception or not.

Fixes PR43374.

Differential Revision: https://reviews.llvm.org/D68463

llvm-svn: 374025

1 files changed, 6 insertions, 6 deletions

diff --git a/llvm/test/CodeGen/ARM/fcmp-xo.ll b/llvm/test/CodeGen/ARM/fcmp-xo.ll
index 8ff3b9017a5..3d5972f0658 100644
--- a/llvm/test/CodeGen/ARM/fcmp-xo.ll
+++ b/llvm/test/CodeGen/ARM/fcmp-xo.ll
@@ -5,7 +5,7 @@
 define arm_aapcs_vfpcc float @foo0(float %a0) local_unnamed_addr {
 ; CHECK-LABEL: foo0:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vcmpe.f32 s0, #0
+; CHECK-NEXT:    vcmp.f32 s0, #0
 ; CHECK-NEXT:    vmov.f32 s2, #5.000000e-01
 ; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-NEXT:    vmov.f32 s4, #-5.000000e-01
@@ -24,7 +24,7 @@ define arm_aapcs_vfpcc float @float1(float %a0) local_unnamed_addr {
 ; CHECK-NEXT:    vmov.f32 s2, #1.000000e+00
 ; CHECK-NEXT:    vmov.f32 s4, #5.000000e-01
 ; CHECK-NEXT:    vmov.f32 s6, #-5.000000e-01
-; CHECK-NEXT:    vcmpe.f32 s2, s0
+; CHECK-NEXT:    vcmp.f32 s2, s0
 ; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-NEXT:    vselgt.f32 s0, s6, s4
 ; CHECK-NEXT:    bx lr
@@ -46,7 +46,7 @@ define arm_aapcs_vfpcc float @float128(float %a0) local_unnamed_addr {
 ; VMOVSR-NEXT:    vmov.f32 s4, #5.000000e-01
 ; VMOVSR-NEXT:    vmov s2, r0
 ; VMOVSR-NEXT:    vmov.f32 s6, #-5.000000e-01
-; VMOVSR-NEXT:    vcmpe.f32 s2, s0
+; VMOVSR-NEXT:    vcmp.f32 s2, s0
 ; VMOVSR-NEXT:    vmrs APSR_nzcv, fpscr
 ; VMOVSR-NEXT:    vselgt.f32 s0, s6, s4
 ; VMOVSR-NEXT:    bx lr
@@ -57,7 +57,7 @@ define arm_aapcs_vfpcc float @float128(float %a0) local_unnamed_addr {
 ; NEON-NEXT:    vmov.f32 s2, #5.000000e-01
 ; NEON-NEXT:    vmov d3, r0, r0
 ; NEON-NEXT:    vmov.f32 s4, #-5.000000e-01
-; NEON-NEXT:    vcmpe.f32 s6, s0
+; NEON-NEXT:    vcmp.f32 s6, s0
 ; NEON-NEXT:    vmrs APSR_nzcv, fpscr
 ; NEON-NEXT:    vselgt.f32 s0, s4, s2
 ; NEON-NEXT:    bx lr
@@ -70,7 +70,7 @@ define arm_aapcs_vfpcc double @double1(double %a0) local_unnamed_addr {
 ; CHECK-LABEL: double1:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vmov.f64 d18, #1.000000e+00
-; CHECK-NEXT:    vcmpe.f64 d18, d0
+; CHECK-NEXT:    vcmp.f64 d18, d0
 ; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-NEXT:    vmov.f64 d16, #5.000000e-01
 ; CHECK-NEXT:    vmov.f64 d17, #-5.000000e-01
@@ -89,7 +89,7 @@ define arm_aapcs_vfpcc double @double128(double %a0) local_unnamed_addr {
 ; CHECK-NEXT:    movt r0, #16480
 ; CHECK-NEXT:    vmov.f64 d16, #5.000000e-01
 ; CHECK-NEXT:    vmov d18, r1, r0
-; CHECK-NEXT:    vcmpe.f64 d18, d0
+; CHECK-NEXT:    vcmp.f64 d18, d0
 ; CHECK-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-NEXT:    vmov.f64 d17, #-5.000000e-01
 ; CHECK-NEXT:    vselgt.f64 d0, d17, d16