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authorChad Rosier <mcrosier@apple.com>2011-12-13 19:22:14 +0000
committerChad Rosier <mcrosier@apple.com>2011-12-13 19:22:14 +0000
commit563de603f71d88cc71a42d5ba79234e7112879a5 (patch)
tree5d3f16cff10dbc4a3ab49661424b4becbb5f01e7 /llvm/test/CodeGen/ARM/fast-isel.ll
parentd47a91ad2a7a88730188624b2b62629f8431078e (diff)
downloadbcm5719-llvm-563de603f71d88cc71a42d5ba79234e7112879a5.tar.gz
bcm5719-llvm-563de603f71d88cc71a42d5ba79234e7112879a5.zip
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
load and then move the result from a GPR to a FPR. llvm-svn: 146502
Diffstat (limited to 'llvm/test/CodeGen/ARM/fast-isel.ll')
-rw-r--r--llvm/test/CodeGen/ARM/fast-isel.ll21
1 files changed, 21 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/fast-isel.ll b/llvm/test/CodeGen/ARM/fast-isel.ll
index 06974608738..7fc080463a3 100644
--- a/llvm/test/CodeGen/ARM/fast-isel.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel.ll
@@ -198,3 +198,24 @@ entry:
ret void
}
+; Check unaligned loads of floats
+%class.TAlignTest = type <{ i16, float }>
+
+define zeroext i1 @test6(%class.TAlignTest* %this) nounwind align 2 {
+entry:
+; ARM: @test6
+; THUMB: @test6
+ %0 = alloca %class.TAlignTest*, align 4
+ store %class.TAlignTest* %this, %class.TAlignTest** %0, align 4
+ %1 = load %class.TAlignTest** %0
+ %2 = getelementptr inbounds %class.TAlignTest* %1, i32 0, i32 1
+ %3 = load float* %2, align 1
+ %4 = fcmp une float %3, 0.000000e+00
+; ARM: ldr r0, [r0, #2]
+; ARM: vmov s0, r0
+; ARM: vcmpe.f32 s0, #0
+; THUMB: ldr.w r0, [r0, #2]
+; THUMB: vmov s0, r0
+; THUMB: vcmpe.f32 s0, #0
+ ret i1 %4
+} \ No newline at end of file
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