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| author | JF Bastien <jfb@google.com> | 2013-06-07 20:10:37 +0000 |
|---|---|---|
| committer | JF Bastien <jfb@google.com> | 2013-06-07 20:10:37 +0000 |
| commit | 06ce03d14137123d2702eb92ff76b7b9f61ce64e (patch) | |
| tree | 717f6a355845d8e76a6f91767d25500d6ca52389 /llvm/test/CodeGen/ARM/fast-isel-conversion.ll | |
| parent | 5ed79566d603c3070055153b4f52630f33558b88 (diff) | |
| download | bcm5719-llvm-06ce03d14137123d2702eb92ff76b7b9f61ce64e.tar.gz bcm5719-llvm-06ce03d14137123d2702eb92ff76b7b9f61ce64e.zip | |
ARM FastISel integer sext/zext improvements
My recent ARM FastISel patch exposed this bug:
http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.
The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.
fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).
2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.
fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.
Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.
I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.
llvm-svn: 183551
Diffstat (limited to 'llvm/test/CodeGen/ARM/fast-isel-conversion.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fast-isel-conversion.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/fast-isel-conversion.ll b/llvm/test/CodeGen/ARM/fast-isel-conversion.ll index 686ccad029d..94654f39d12 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-conversion.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-conversion.ll @@ -130,11 +130,11 @@ entry: define void @uitofp_single_i8(i8 %a) nounwind ssp { entry: ; ARM: uitofp_single_i8 -; ARM: uxtb r0, r0 +; ARM: and r0, r0, #255 ; ARM: vmov s0, r0 ; ARM: vcvt.f32.u32 s0, s0 ; THUMB: uitofp_single_i8 -; THUMB: uxtb r0, r0 +; THUMB: and r0, r0, #255 ; THUMB: vmov s0, r0 ; THUMB: vcvt.f32.u32 s0, s0 %b.addr = alloca float, align 4 @@ -176,11 +176,11 @@ entry: define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp { entry: ; ARM: uitofp_double_i8 -; ARM: uxtb r0, r0 +; ARM: and r0, r0, #255 ; ARM: vmov s0, r0 ; ARM: vcvt.f64.u32 d16, s0 ; THUMB: uitofp_double_i8 -; THUMB: uxtb r0, r0 +; THUMB: and r0, r0, #255 ; THUMB: vmov s0, r0 ; THUMB: vcvt.f64.u32 d16, s0 %b.addr = alloca double, align 8 |
