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| author | Matthias Braun <matze@braunis.de> | 2018-10-29 20:10:42 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2018-10-29 20:10:42 +0000 |
| commit | c045c557b07a084a5dc2de336fdc807e87589963 (patch) | |
| tree | b692258804b21aa2c4c55d9b937dbc84c9c47f7a /llvm/test/CodeGen/ARM/fast-isel-align.ll | |
| parent | 49b8ac0a3d164fca82d6cfb06d6c99705b97c76d (diff) | |
| download | bcm5719-llvm-c045c557b07a084a5dc2de336fdc807e87589963.tar.gz bcm5719-llvm-c045c557b07a084a5dc2de336fdc807e87589963.zip | |
Relax fast register allocator related test cases; NFC
- Relex hard coded registers and stack frame sizes
- Some test cleanups
- Change phi-dbg.ll to match on mir output after phi elimination instead
of going through the whole codegen pipeline.
This is in preparation for https://reviews.llvm.org/D52010
I'm committing all the test changes upfront that work before and after
independently.
llvm-svn: 345532
Diffstat (limited to 'llvm/test/CodeGen/ARM/fast-isel-align.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fast-isel-align.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/fast-isel-align.ll b/llvm/test/CodeGen/ARM/fast-isel-align.ll index 71cd73a4a25..9dab0abedb6 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-align.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-align.ll @@ -26,12 +26,12 @@ define void @unaligned_store(float %x, float %y) nounwind { entry: ; ARM: @unaligned_store -; ARM: vmov r1, s0 -; ARM: str r1, [r0] +; ARM: vmov [[REG:r[0-9]+]], s0 +; ARM: str [[REG]], [{{r[0-9]+}}] ; THUMB: @unaligned_store -; THUMB: vmov r1, s0 -; THUMB: str r1, [r0] +; THUMB: vmov [[REG:r[0-9]+]], s0 +; THUMB: str [[REG]], [{{r[0-9]+}}] %add = fadd float %x, %y %0 = load %struct.anon*, %struct.anon** @a, align 4 |
