[ARM] Implement execute-only support in CodeGen

This implements execute-only support for ARM code generation, which
prevents the compiler from generating data accesses to code sections.
The following changes are involved:

* Add the CodeGen option "-arm-execute-only" to the ARM code generator.
* Add the clang flag "-mexecute-only" as well as the GCC-compatible
  alias "-mpure-code" to enable this option.
* When enabled, literal pools are replaced with MOVW/MOVT instructions,
  with VMOV used in addition for floating-point literals. As the MOVT
  instruction is required, execute-only support is only available in
  Thumb mode for targets supporting ARMv8-M baseline or Thumb2.
* Jump tables are placed in data sections when in execute-only mode.
* The execute-only text section is assigned section ID 0, and is
  marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'.
  This also overrides selection of ELF sections for globals.

llvm-svn: 289784

1 files changed, 46 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/ARM/execute-only-big-stack-frame.ll b/llvm/test/CodeGen/ARM/execute-only-big-stack-frame.ll
new file mode 100644
index 00000000000..fb498a81e39
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/execute-only-big-stack-frame.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -mtriple=thumbv7m -arm-execute-only -O0 %s -o - \
+; RUN:  | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
+; RUN: llc < %s -mtriple=thumbv8m.base -arm-execute-only -O0 %s -o - \
+; RUN:  | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
+; RUN: llc < %s -mtriple=thumbv8m.main -arm-execute-only -O0 %s -o - \
+; RUN:  | FileCheck --check-prefix=CHECK-SUBW-ADDW %s
+
+define i8 @test_big_stack_frame() {
+; CHECK-SUBW-ADDW-LABEL: test_big_stack_frame:
+; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-SUBW-ADDW:       sub.w sp, sp, #65536
+; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-SUBW-ADDW:       add.w [[REG1:r[0-9]+]], sp, #255
+; CHECK-SUBW-ADDW:       add.w {{r[0-9]+}}, [[REG1]], #65280
+; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-SUBW-ADDW:       add.w lr, sp, #61440
+; CHECK-SUBW-ADDW-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-SUBW-ADDW:       add.w sp, sp, #65536
+
+; CHECK-MOVW-MOVT-ADD-LABEL: test_big_stack_frame:
+; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-MOVW-MOVT-ADD:       movw [[REG1:r[0-9]+]], #0
+; CHECK-MOVW-MOVT-ADD:       movt [[REG1]], #65535
+; CHECK-MOVW-MOVT-ADD:       add sp, [[REG1]]
+; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-MOVW-MOVT-ADD:       movw [[REG2:r[0-9]+]], #65532
+; CHECK-MOVW-MOVT-ADD:       movt [[REG2]], #0
+; CHECK-MOVW-MOVT-ADD:       add [[REG2]], sp
+; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-MOVW-MOVT-ADD:       movw [[REG3:r[0-9]+]], #65532
+; CHECK-MOVW-MOVT-ADD:       movt [[REG3]], #0
+; CHECK-MOVW-MOVT-ADD:       add [[REG3]], sp
+; CHECK-MOVW-MOVT-ADD-NOT:   ldr {{r[0-9]+}}, .{{.*}}
+; CHECK-MOVW-MOVT-ADD:       movw [[REG4:r[0-9]+]], #0
+; CHECK-MOVW-MOVT-ADD:       movt [[REG4]], #1
+; CHECK-MOVW-MOVT-ADD:       add sp, [[REG4]]
+
+entry:
+  %s1 = alloca i8
+  %buffer = alloca [65528 x i8], align 1
+  call void @foo(i8* %s1)
+  %load = load i8, i8* %s1
+  ret i8 %load
+}
+
+declare void @foo(i8*)