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| author | Javed Absar <javed.absar@arm.com> | 2015-04-09 14:07:28 +0000 |
|---|---|---|
| committer | Javed Absar <javed.absar@arm.com> | 2015-04-09 14:07:28 +0000 |
| commit | 5c5e3c5e36aaf420aad69f0e30909b3f6bfecf10 (patch) | |
| tree | dc7edf89413eaee94d31e678e25467bf7184ddb6 /llvm/test/CodeGen/ARM/div.ll | |
| parent | 2b391694bf455beef714ce43076b05f6708b7f86 (diff) | |
| download | bcm5719-llvm-5c5e3c5e36aaf420aad69f0e30909b3f6bfecf10.tar.gz bcm5719-llvm-5c5e3c5e36aaf420aad69f0e30909b3f6bfecf10.zip | |
[ARM] support for Cortex-R4/R4F
Currently, llvm (backend) doesn't know cortex-r4, even though it is the
default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes
'cortex-r4' is not a recognized processor for this target' by llvm.
This patch adds support for cortex-r4 and, very closely related, r4f.
llvm-svn: 234486
Diffstat (limited to 'llvm/test/CodeGen/ARM/div.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/div.ll | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/llvm/test/CodeGen/ARM/div.ll b/llvm/test/CodeGen/ARM/div.ll index a339c816c57..7b298fee42a 100644 --- a/llvm/test/CodeGen/ARM/div.ll +++ b/llvm/test/CodeGen/ARM/div.ll @@ -1,11 +1,13 @@ -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4 | FileCheck %s -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f | FileCheck %s -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV define i32 @f1(i32 %a, i32 %b) { entry: -; CHECK-ARM: f1 -; CHECK-ARM: __divsi3 +; CHECK-SWDIV: f1 +; CHECK-SWDIV: __divsi3 ; CHECK-HWDIV: f1 ; CHECK-HWDIV: sdiv @@ -15,8 +17,8 @@ entry: define i32 @f2(i32 %a, i32 %b) { entry: -; CHECK-ARM: f2 -; CHECK-ARM: __udivsi3 +; CHECK-SWDIV: f2 +; CHECK-SWDIV: __udivsi3 ; CHECK-HWDIV: f2 ; CHECK-HWDIV: udiv @@ -26,8 +28,8 @@ entry: define i32 @f3(i32 %a, i32 %b) { entry: -; CHECK-ARM: f3 -; CHECK-ARM: __modsi3 +; CHECK-SWDIV: f3 +; CHECK-SWDIV: __modsi3 ; CHECK-HWDIV: f3 ; CHECK-HWDIV: sdiv @@ -38,8 +40,8 @@ entry: define i32 @f4(i32 %a, i32 %b) { entry: -; CHECK-ARM: f4 -; CHECK-ARM: __umodsi3 +; CHECK-SWDIV: f4 +; CHECK-SWDIV: __umodsi3 ; CHECK-HWDIV: f4 ; CHECK-HWDIV: udiv |
