Cortex-R5 can issue Thumb2 integer division instructions.

llvm-svn: 183275

1 files changed, 12 insertions, 11 deletions

diff --git a/llvm/test/CodeGen/ARM/div.ll b/llvm/test/CodeGen/ARM/div.ll
index 82cfca182b8..a339c816c57 100644
--- a/llvm/test/CodeGen/ARM/div.ll
+++ b/llvm/test/CodeGen/ARM/div.ll
@@ -1,13 +1,14 @@
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM
-; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift     | FileCheck %s -check-prefix=CHECK-SWIFT
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift     | FileCheck %s -check-prefix=CHECK-HWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV
 
 define i32 @f1(i32 %a, i32 %b) {
 entry:
 ; CHECK-ARM: f1
 ; CHECK-ARM: __divsi3
 
-; CHECK-SWIFT: f1
-; CHECK-SWIFT: sdiv
+; CHECK-HWDIV: f1
+; CHECK-HWDIV: sdiv
         %tmp1 = sdiv i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
@@ -17,8 +18,8 @@ entry:
 ; CHECK-ARM: f2
 ; CHECK-ARM: __udivsi3
 
-; CHECK-SWIFT: f2
-; CHECK-SWIFT: udiv
+; CHECK-HWDIV: f2
+; CHECK-HWDIV: udiv
         %tmp1 = udiv i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
@@ -28,9 +29,9 @@ entry:
 ; CHECK-ARM: f3
 ; CHECK-ARM: __modsi3
 
-; CHECK-SWIFT: f3
-; CHECK-SWIFT: sdiv
-; CHECK-SWIFT: mls
+; CHECK-HWDIV: f3
+; CHECK-HWDIV: sdiv
+; CHECK-HWDIV: mls
         %tmp1 = srem i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
@@ -40,9 +41,9 @@ entry:
 ; CHECK-ARM: f4
 ; CHECK-ARM: __umodsi3
 
-; CHECK-SWIFT: f4
-; CHECK-SWIFT: udiv
-; CHECK-SWIFT: mls
+; CHECK-HWDIV: f4
+; CHECK-HWDIV: udiv
+; CHECK-HWDIV: mls
         %tmp1 = urem i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }