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| author | Oliver Stannard <oliver.stannard@arm.com> | 2016-08-08 15:28:31 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2016-08-08 15:28:31 +0000 |
| commit | 8331aaee8fb9172ddf0cb45c4b04cb76fe224da4 (patch) | |
| tree | c5549f749c7cf270e5e3b0c5cfc25490a0fad3d3 /llvm/test/CodeGen/ARM/build-attributes.ll | |
| parent | 219feac45643d92784186bcee627d940775b596b (diff) | |
| download | bcm5719-llvm-8331aaee8fb9172ddf0cb45c4b04cb76fe224da4.tar.gz bcm5719-llvm-8331aaee8fb9172ddf0cb45c4b04cb76fe224da4.zip | |
[ARM] Add support for embedded position-independent code
This patch adds support for some new relocation models to the ARM
backend:
* Read-only position independence (ROPI): Code and read-only data is accessed
PC-relative. The offsets between all code and RO data sections are known at
static link time. This does not affect read-write data.
* Read-write position independence (RWPI): Read-write data is accessed relative
to the static base register (r9). The offsets between all writeable data
sections are known at static link time. This does not affect read-only data.
These two modes are independent (they specify how different objects
should be addressed), so they can be used individually or together. They
are otherwise the same as the "static" relocation model, and are not
compatible with SysV-style PIC using a global offset table.
These modes are normally used by bare-metal systems or systems with
small real-time operating systems. They are designed to avoid the need
for a dynamic linker, the only initialisation required is setting r9 to
an appropriate value for RWPI code.
I have only added support to SelectionDAG, not FastISel, because
FastISel is currently disabled for bare-metal targets where these modes
would be used.
Differential Revision: https://reviews.llvm.org/D23195
llvm-svn: 278015
Diffstat (limited to 'llvm/test/CodeGen/ARM/build-attributes.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/build-attributes.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll index 990db8a00c4..53b8fc39a7c 100644 --- a/llvm/test/CodeGen/ARM/build-attributes.ll +++ b/llvm/test/CodeGen/ARM/build-attributes.ll @@ -147,6 +147,9 @@ ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=RELOC-OTHER ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=PCS-R9-USE ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+reserve-r9,+strict-align | FileCheck %s --check-prefix=PCS-R9-RESERVE +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=ropi | FileCheck %s --check-prefix=RELOC-ROPI +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=rwpi | FileCheck %s --check-prefix=RELOC-RWPI +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=ropi-rwpi | FileCheck %s --check-prefix=RELOC-ROPI-RWPI ; ARMv8.1a (AArch32) ; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi | FileCheck %s --check-prefix=NO-STRICT-ALIGN @@ -1522,6 +1525,15 @@ ; RELOC-PIC: .eabi_attribute 16, 1 ; RELOC-PIC: .eabi_attribute 17, 2 ; RELOC-OTHER: .eabi_attribute 17, 1 +; RELOC-ROPI-NOT: .eabi_attribute 15, +; RELOC-ROPI: .eabi_attribute 16, 1 +; RELOC-ROPI: .eabi_attribute 17, 1 +; RELOC-RWPI: .eabi_attribute 15, 2 +; RELOC-RWPI-NOT: .eabi_attribute 16, +; RELOC-RWPI: .eabi_attribute 17, 1 +; RELOC-ROPI-RWPI: .eabi_attribute 15, 2 +; RELOC-ROPI-RWPI: .eabi_attribute 16, 1 +; RELOC-ROPI-RWPI: .eabi_attribute 17, 1 ; PCS-R9-USE: .eabi_attribute 14, 0 ; PCS-R9-RESERVE: .eabi_attribute 14, 3 |
