[ARM] Add hardware build attributes in assembler

In the assembler, we should emit build attributes based on the target
selected with command-line options. This matches the GNU assembler's
behaviour. We only do this for build attributes which describe the
hardware that is expected to be available, not the ones that describe
ABI compatibility.

This is done by moving some of the attribute emission code to
ARMTargetStreamer, so that it can be shared between the assembly and
code-generation code paths. Since the assembler only creates a
MCSubtargetInfo, not an ARMSubtarget, the code had to be changed to
check raw features, and not use the convenience functions in
ARMSubtarget.

If different attributes are later specified using the .eabi_attribute
directive, then they will take precedence, as happens when the same
.eabi_attribute is specified twice.

This must be enabled by an option, because we don't want to do this when
parsing inline assembly. The attributes would match the ones emitted at
the start of the file, so wouldn't actually change the emitted object
file, but the extra directives would be added to every inline assembly
block when emitting assembly, which we'd like to avoid.

The majority of the changes in the build-attributes.ll test are just
re-ordering the directives, because the hardware attributes are now
emitted before the ABI ones. However, I did fix one bug which I spotted:
Tag_CPU_arch_profile was not being emitted for v6M.

Differential revision: https://reviews.llvm.org/D31812

llvm-svn: 300547

1 files changed, 227 insertions, 234 deletions

diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll
index fc85a3a2e68..699ef6e92a4 100644
--- a/llvm/test/CodeGen/ARM/build-attributes.ll
+++ b/llvm/test/CodeGen/ARM/build-attributes.ll
@@ -231,6 +231,11 @@
 ; V6:   .eabi_attribute 6, 6
 ; V6:   .eabi_attribute 8, 1
 ;; We assume round-to-nearest by default (matches GCC)
+; V6-NOT:   .eabi_attribute 27
+; V6-NOT:    .eabi_attribute 36
+; V6-NOT:    .eabi_attribute 42
+; V6-NOT:  .eabi_attribute 44
+; V6-NOT:    .eabi_attribute 68
 ; V6-NOT:   .eabi_attribute 19
 ;; The default choice made by llc is for a V6 CPU without an FPU.
 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
@@ -242,13 +247,8 @@
 ; V6:   .eabi_attribute 23, 3
 ; V6:   .eabi_attribute 24, 1
 ; V6:   .eabi_attribute 25, 1
-; V6-NOT:   .eabi_attribute 27
 ; V6-NOT:   .eabi_attribute 28
-; V6-NOT:    .eabi_attribute 36
 ; V6:    .eabi_attribute 38, 1
-; V6-NOT:    .eabi_attribute 42
-; V6-NOT:  .eabi_attribute 44
-; V6-NOT:    .eabi_attribute 68
 
 ; V6-FAST-NOT:   .eabi_attribute 19
 ;; Despite the V6 CPU having no FPU by default, we chose to flush to
@@ -262,9 +262,14 @@
 ;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
 ;; V6-M, however we don't model the OS extension so this is fine.
 ; V6M:  .eabi_attribute 6, 12
-; V6M-NOT:  .eabi_attribute 7
+; V6M:  .eabi_attribute 7, 77
 ; V6M:  .eabi_attribute 8, 0
 ; V6M:  .eabi_attribute 9, 1
+; V6M-NOT:  .eabi_attribute 27
+; V6M-NOT:  .eabi_attribute 36
+; V6M-NOT:  .eabi_attribute 42
+; V6M-NOT:  .eabi_attribute 44
+; V6M-NOT:  .eabi_attribute 68
 ; V6M-NOT:   .eabi_attribute 19
 ;; The default choice made by llc is for a V6M CPU without an FPU.
 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
@@ -276,13 +281,8 @@
 ; V6M:   .eabi_attribute 23, 3
 ; V6M:  .eabi_attribute 24, 1
 ; V6M:  .eabi_attribute 25, 1
-; V6M-NOT:  .eabi_attribute 27
 ; V6M-NOT:  .eabi_attribute 28
-; V6M-NOT:  .eabi_attribute 36
 ; V6M:  .eabi_attribute 38, 1
-; V6M-NOT:  .eabi_attribute 42
-; V6M-NOT:  .eabi_attribute 44
-; V6M-NOT:  .eabi_attribute 68
 
 ; V6M-FAST-NOT:   .eabi_attribute 19
 ;; Despite the V6M CPU having no FPU by default, we chose to flush to
@@ -298,6 +298,11 @@
 ; ARM1156T2F-S: .eabi_attribute 8, 1
 ; ARM1156T2F-S: .eabi_attribute 9, 2
 ; ARM1156T2F-S: .fpu vfpv2
+; ARM1156T2F-S-NOT: .eabi_attribute 27
+; ARM1156T2F-S-NOT: .eabi_attribute 36
+; ARM1156T2F-S-NOT:    .eabi_attribute 42
+; ARM1156T2F-S-NOT:    .eabi_attribute 44
+; ARM1156T2F-S-NOT:    .eabi_attribute 68
 ; ARM1156T2F-S-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; ARM1156T2F-S: .eabi_attribute 20, 1
@@ -306,13 +311,8 @@
 ; ARM1156T2F-S: .eabi_attribute 23, 3
 ; ARM1156T2F-S: .eabi_attribute 24, 1
 ; ARM1156T2F-S: .eabi_attribute 25, 1
-; ARM1156T2F-S-NOT: .eabi_attribute 27
 ; ARM1156T2F-S-NOT: .eabi_attribute 28
-; ARM1156T2F-S-NOT: .eabi_attribute 36
 ; ARM1156T2F-S: .eabi_attribute 38, 1
-; ARM1156T2F-S-NOT:    .eabi_attribute 42
-; ARM1156T2F-S-NOT:    .eabi_attribute 44
-; ARM1156T2F-S-NOT:    .eabi_attribute 68
 
 ; ARM1156T2F-S-FAST-NOT:   .eabi_attribute 19
 ;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
@@ -327,6 +327,11 @@
 ; V7M:  .eabi_attribute 7, 77
 ; V7M:  .eabi_attribute 8, 0
 ; V7M:  .eabi_attribute 9, 2
+; V7M-NOT:  .eabi_attribute 27
+; V7M-NOT:  .eabi_attribute 36
+; V7M-NOT:  .eabi_attribute 42
+; V7M-NOT:  .eabi_attribute 44
+; V7M-NOT:  .eabi_attribute 68
 ; V7M-NOT:   .eabi_attribute 19
 ;; The default choice made by llc is for a V7M CPU without an FPU.
 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
@@ -338,13 +343,8 @@
 ; V7M: .eabi_attribute 23, 3
 ; V7M:  .eabi_attribute 24, 1
 ; V7M:  .eabi_attribute 25, 1
-; V7M-NOT:  .eabi_attribute 27
 ; V7M-NOT:  .eabi_attribute 28
-; V7M-NOT:  .eabi_attribute 36
 ; V7M:  .eabi_attribute 38, 1
-; V7M-NOT:  .eabi_attribute 42
-; V7M-NOT:  .eabi_attribute 44
-; V7M-NOT:  .eabi_attribute 68
 
 ; V7M-FAST-NOT:   .eabi_attribute 19
 ;; Despite the V7M CPU having no FPU by default, we chose to flush
@@ -357,6 +357,11 @@
 
 ; V7:      .syntax unified
 ; V7: .eabi_attribute 6, 10
+; V7-NOT: .eabi_attribute 27
+; V7-NOT: .eabi_attribute 36
+; V7-NOT:    .eabi_attribute 42
+; V7-NOT:    .eabi_attribute 44
+; V7-NOT:    .eabi_attribute 68
 ; V7-NOT:   .eabi_attribute 19
 ;; In safe-maths mode we default to an IEEE 754 compliant choice.
 ; V7: .eabi_attribute 20, 1
@@ -365,13 +370,8 @@
 ; V7: .eabi_attribute 23, 3
 ; V7: .eabi_attribute 24, 1
 ; V7: .eabi_attribute 25, 1
-; V7-NOT: .eabi_attribute 27
 ; V7-NOT: .eabi_attribute 28
-; V7-NOT: .eabi_attribute 36
 ; V7: .eabi_attribute 38, 1
-; V7-NOT:    .eabi_attribute 42
-; V7-NOT:    .eabi_attribute 44
-; V7-NOT:    .eabi_attribute 68
 
 ; V7-FAST-NOT:   .eabi_attribute 19
 ;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
@@ -386,6 +386,9 @@
 ; V7VE: .eabi_attribute 7, 65   @ Tag_CPU_arch_profile
 ; V7VE: .eabi_attribute 8, 1    @ Tag_ARM_ISA_use
 ; V7VE: .eabi_attribute 9, 2    @ Tag_THUMB_ISA_use
+; V7VE: .eabi_attribute 42, 1   @ Tag_MPextension_use
+; V7VE: .eabi_attribute 44, 2   @ Tag_DIV_use
+; V7VE: .eabi_attribute 68, 3   @ Tag_Virtualization_use
 ; V7VE: .eabi_attribute 17, 1   @ Tag_ABI_PCS_GOT_use
 ; V7VE: .eabi_attribute 20, 1   @ Tag_ABI_FP_denormal
 ; V7VE: .eabi_attribute 21, 1   @ Tag_ABI_FP_exceptions
@@ -393,19 +396,16 @@
 ; V7VE: .eabi_attribute 24, 1   @ Tag_ABI_align_needed
 ; V7VE: .eabi_attribute 25, 1   @ Tag_ABI_align_preserved
 ; V7VE: .eabi_attribute 38, 1   @ Tag_ABI_FP_16bit_format
-; V7VE: .eabi_attribute 42, 1   @ Tag_MPextension_use
-; V7VE: .eabi_attribute 44, 2   @ Tag_DIV_use
-; V7VE: .eabi_attribute 68, 3   @ Tag_Virtualization_use
 
 ; V8:      .syntax unified
 ; V8: .eabi_attribute 67, "2.09"
 ; V8: .eabi_attribute 6, 14
+; V8-NOT: .eabi_attribute 44
 ; V8-NOT:   .eabi_attribute 19
 ; V8: .eabi_attribute 20, 1
 ; V8: .eabi_attribute 21, 1
 ; V8-NOT: .eabi_attribute 22
 ; V8: .eabi_attribute 23, 3
-; V8-NOT: .eabi_attribute 44
 
 ; V8-FAST-NOT:   .eabi_attribute 19
 ;; The default does have an FPU, and for V8-A, it flushes preserving sign.
@@ -496,6 +496,30 @@
 ; CORTEX-A7-FPUV4: .fpu vfpv4
 
 ; CORTEX-A7-CHECK-NOT:   .eabi_attribute 19
+
+; Tag_FP_HP_extension
+; CORTEX-A7-CHECK: .eabi_attribute      36, 1
+; CORTEX-A7-NOFPU-NOT: .eabi_attribute  36
+; CORTEX-A7-FPUV4: .eabi_attribute      36, 1
+
+; Tag_MPextension_use
+; CORTEX-A7-CHECK: .eabi_attribute      42, 1
+; CORTEX-A7-NOFPU: .eabi_attribute      42, 1
+; CORTEX-A7-FPUV4: .eabi_attribute      42, 1
+
+; Tag_DIV_use
+; CORTEX-A7-CHECK: .eabi_attribute      44, 2
+; CORTEX-A7-NOFPU: .eabi_attribute      44, 2
+; CORTEX-A7-FPUV4: .eabi_attribute      44, 2
+
+; Tag_DSP_extension
+; CORTEX-A7-CHECK-NOT: .eabi_attribute      46
+
+; Tag_Virtualization_use
+; CORTEX-A7-CHECK: .eabi_attribute      68, 3
+; CORTEX-A7-NOFPU: .eabi_attribute      68, 3
+; CORTEX-A7-FPUV4: .eabi_attribute      68, 3
+
 ; Tag_ABI_FP_denormal
 ;; We default to IEEE 754 compliance
 ; CORTEX-A7-CHECK: .eabi_attribute      20, 1
@@ -535,40 +559,20 @@
 ; CORTEX-A7-NOFPU: .eabi_attribute      25, 1
 ; CORTEX-A7-FPUV4: .eabi_attribute      25, 1
 
-; Tag_FP_HP_extension
-; CORTEX-A7-CHECK: .eabi_attribute      36, 1
-; CORTEX-A7-NOFPU-NOT: .eabi_attribute  36
-; CORTEX-A7-FPUV4: .eabi_attribute      36, 1
-
 ; Tag_FP_16bit_format
 ; CORTEX-A7-CHECK: .eabi_attribute      38, 1
 ; CORTEX-A7-NOFPU: .eabi_attribute      38, 1
 ; CORTEX-A7-FPUV4: .eabi_attribute      38, 1
 
-; Tag_MPextension_use
-; CORTEX-A7-CHECK: .eabi_attribute      42, 1
-; CORTEX-A7-NOFPU: .eabi_attribute      42, 1
-; CORTEX-A7-FPUV4: .eabi_attribute      42, 1
-
-; Tag_DIV_use
-; CORTEX-A7-CHECK: .eabi_attribute      44, 2
-; CORTEX-A7-NOFPU: .eabi_attribute      44, 2
-; CORTEX-A7-FPUV4: .eabi_attribute      44, 2
-
-; Tag_DSP_extension
-; CORTEX-A7-CHECK-NOT: .eabi_attribute      46
-
-; Tag_Virtualization_use
-; CORTEX-A7-CHECK: .eabi_attribute      68, 3
-; CORTEX-A7-NOFPU: .eabi_attribute      68, 3
-; CORTEX-A7-FPUV4: .eabi_attribute      68, 3
-
 ; CORTEX-A5-DEFAULT:        .cpu    cortex-a5
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 6, 10
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 7, 65
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 8, 1
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 9, 2
 ; CORTEX-A5-DEFAULT:        .fpu    neon-vfpv4
+; CORTEX-A5-DEFAULT:        .eabi_attribute 42, 1
+; CORTEX-A5-DEFAULT-NOT:        .eabi_attribute 44
+; CORTEX-A5-DEFAULT:        .eabi_attribute 68, 1
 ; CORTEX-A5-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 20, 1
@@ -577,9 +581,6 @@
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 23, 3
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 24, 1
 ; CORTEX-A5-DEFAULT:        .eabi_attribute 25, 1
-; CORTEX-A5-DEFAULT:        .eabi_attribute 42, 1
-; CORTEX-A5-DEFAULT-NOT:        .eabi_attribute 44
-; CORTEX-A5-DEFAULT:        .eabi_attribute 68, 1
 
 ; CORTEX-A5-DEFAULT-FAST-NOT:   .eabi_attribute 19
 ;; The A5 defaults to a VFPv4 FPU, so it flushed preserving the sign when -ffast-math
@@ -595,6 +596,8 @@
 ; CORTEX-A5-NONEON:        .eabi_attribute 8, 1
 ; CORTEX-A5-NONEON:        .eabi_attribute 9, 2
 ; CORTEX-A5-NONEON:        .fpu    vfpv4-d16
+; CORTEX-A5-NONEON:        .eabi_attribute 42, 1
+; CORTEX-A5-NONEON:        .eabi_attribute 68, 1
 ;; We default to IEEE 754 compliance
 ; CORTEX-A5-NONEON:        .eabi_attribute 20, 1
 ; CORTEX-A5-NONEON:        .eabi_attribute 21, 1
@@ -602,8 +605,6 @@
 ; CORTEX-A5-NONEON:        .eabi_attribute 23, 3
 ; CORTEX-A5-NONEON:        .eabi_attribute 24, 1
 ; CORTEX-A5-NONEON:        .eabi_attribute 25, 1
-; CORTEX-A5-NONEON:        .eabi_attribute 42, 1
-; CORTEX-A5-NONEON:        .eabi_attribute 68, 1
 
 ; CORTEX-A5-NONEON-FAST-NOT:   .eabi_attribute 19
 ;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
@@ -619,6 +620,8 @@
 ; CORTEX-A5-NOFPU:        .eabi_attribute 8, 1
 ; CORTEX-A5-NOFPU:        .eabi_attribute 9, 2
 ; CORTEX-A5-NOFPU-NOT:    .fpu
+; CORTEX-A5-NOFPU:        .eabi_attribute 42, 1
+; CORTEX-A5-NOFPU:        .eabi_attribute 68, 1
 ; CORTEX-A5-NOFPU-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A5-NOFPU:        .eabi_attribute 20, 1
@@ -627,8 +630,6 @@
 ; CORTEX-A5-NOFPU:        .eabi_attribute 23, 3
 ; CORTEX-A5-NOFPU:        .eabi_attribute 24, 1
 ; CORTEX-A5-NOFPU:        .eabi_attribute 25, 1
-; CORTEX-A5-NOFPU:        .eabi_attribute 42, 1
-; CORTEX-A5-NOFPU:        .eabi_attribute 68, 1
 
 ; CORTEX-A5-NOFPU-FAST-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
@@ -645,6 +646,11 @@
 ; CORTEX-A8-SOFT:  .eabi_attribute 8, 1
 ; CORTEX-A8-SOFT:  .eabi_attribute 9, 2
 ; CORTEX-A8-SOFT:  .fpu neon
+; CORTEX-A8-SOFT-NOT:  .eabi_attribute 27
+; CORTEX-A8-SOFT-NOT:  .eabi_attribute 36, 1
+; CORTEX-A8-SOFT-NOT:  .eabi_attribute 42, 1
+; CORTEX-A8-SOFT-NOT:  .eabi_attribute 44
+; CORTEX-A8-SOFT:  .eabi_attribute 68, 1
 ; CORTEX-A8-SOFT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A8-SOFT:  .eabi_attribute 20, 1
@@ -653,13 +659,8 @@
 ; CORTEX-A8-SOFT:  .eabi_attribute 23, 3
 ; CORTEX-A8-SOFT:  .eabi_attribute 24, 1
 ; CORTEX-A8-SOFT:  .eabi_attribute 25, 1
-; CORTEX-A8-SOFT-NOT:  .eabi_attribute 27
 ; CORTEX-A8-SOFT-NOT:  .eabi_attribute 28
-; CORTEX-A8-SOFT-NOT:  .eabi_attribute 36, 1
 ; CORTEX-A8-SOFT:  .eabi_attribute 38, 1
-; CORTEX-A8-SOFT-NOT:  .eabi_attribute 42, 1
-; CORTEX-A8-SOFT-NOT:  .eabi_attribute 44
-; CORTEX-A8-SOFT:  .eabi_attribute 68, 1
 
 ; CORTEX-A9-SOFT:  .cpu cortex-a9
 ; CORTEX-A9-SOFT:  .eabi_attribute 6, 10
@@ -667,6 +668,11 @@
 ; CORTEX-A9-SOFT:  .eabi_attribute 8, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 9, 2
 ; CORTEX-A9-SOFT:  .fpu neon
+; CORTEX-A9-SOFT-NOT:  .eabi_attribute 27
+; CORTEX-A9-SOFT:  .eabi_attribute 36, 1
+; CORTEX-A9-SOFT:  .eabi_attribute 42, 1
+; CORTEX-A9-SOFT-NOT:  .eabi_attribute 44
+; CORTEX-A9-SOFT:  .eabi_attribute 68, 1
 ; CORTEX-A9-SOFT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A9-SOFT:  .eabi_attribute 20, 1
@@ -675,13 +681,8 @@
 ; CORTEX-A9-SOFT:  .eabi_attribute 23, 3
 ; CORTEX-A9-SOFT:  .eabi_attribute 24, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 25, 1
-; CORTEX-A9-SOFT-NOT:  .eabi_attribute 27
 ; CORTEX-A9-SOFT-NOT:  .eabi_attribute 28
-; CORTEX-A9-SOFT:  .eabi_attribute 36, 1
 ; CORTEX-A9-SOFT:  .eabi_attribute 38, 1
-; CORTEX-A9-SOFT:  .eabi_attribute 42, 1
-; CORTEX-A9-SOFT-NOT:  .eabi_attribute 44
-; CORTEX-A9-SOFT:  .eabi_attribute 68, 1
 
 ; CORTEX-A8-SOFT-FAST-NOT:   .eabi_attribute 19
 ; CORTEX-A9-SOFT-FAST-NOT:   .eabi_attribute 19
@@ -699,6 +700,10 @@
 ; CORTEX-A8-HARD:  .eabi_attribute 8, 1
 ; CORTEX-A8-HARD:  .eabi_attribute 9, 2
 ; CORTEX-A8-HARD:  .fpu neon
+; CORTEX-A8-HARD-NOT:  .eabi_attribute 27
+; CORTEX-A8-HARD-NOT:  .eabi_attribute 36, 1
+; CORTEX-A8-HARD-NOT:  .eabi_attribute 42, 1
+; CORTEX-A8-HARD:  .eabi_attribute 68, 1
 ; CORTEX-A8-HARD-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A8-HARD:  .eabi_attribute 20, 1
@@ -707,12 +712,8 @@
 ; CORTEX-A8-HARD:  .eabi_attribute 23, 3
 ; CORTEX-A8-HARD:  .eabi_attribute 24, 1
 ; CORTEX-A8-HARD:  .eabi_attribute 25, 1
-; CORTEX-A8-HARD-NOT:  .eabi_attribute 27
 ; CORTEX-A8-HARD:  .eabi_attribute 28, 1
-; CORTEX-A8-HARD-NOT:  .eabi_attribute 36, 1
 ; CORTEX-A8-HARD:  .eabi_attribute 38, 1
-; CORTEX-A8-HARD-NOT:  .eabi_attribute 42, 1
-; CORTEX-A8-HARD:  .eabi_attribute 68, 1
 
 
 
@@ -722,6 +723,10 @@
 ; CORTEX-A9-HARD:  .eabi_attribute 8, 1
 ; CORTEX-A9-HARD:  .eabi_attribute 9, 2
 ; CORTEX-A9-HARD:  .fpu neon
+; CORTEX-A9-HARD-NOT:  .eabi_attribute 27
+; CORTEX-A9-HARD:  .eabi_attribute 36, 1
+; CORTEX-A9-HARD:  .eabi_attribute 42, 1
+; CORTEX-A9-HARD:  .eabi_attribute 68, 1
 ; CORTEX-A9-HARD-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A9-HARD:  .eabi_attribute 20, 1
@@ -730,12 +735,8 @@
 ; CORTEX-A9-HARD:  .eabi_attribute 23, 3
 ; CORTEX-A9-HARD:  .eabi_attribute 24, 1
 ; CORTEX-A9-HARD:  .eabi_attribute 25, 1
-; CORTEX-A9-HARD-NOT:  .eabi_attribute 27
 ; CORTEX-A9-HARD:  .eabi_attribute 28, 1
-; CORTEX-A9-HARD:  .eabi_attribute 36, 1
 ; CORTEX-A9-HARD:  .eabi_attribute 38, 1
-; CORTEX-A9-HARD:  .eabi_attribute 42, 1
-; CORTEX-A9-HARD:  .eabi_attribute 68, 1
 
 ; CORTEX-A8-HARD-FAST-NOT:   .eabi_attribute 19
 ;; The A8 defaults to a VFPv3 FPU, so it flushes preserving the sign when
@@ -759,6 +760,9 @@
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 8, 1
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 9, 2
 ; CORTEX-A12-DEFAULT:  .fpu neon-vfpv4
+; CORTEX-A12-DEFAULT:  .eabi_attribute 42, 1
+; CORTEX-A12-DEFAULT:  .eabi_attribute 44, 2
+; CORTEX-A12-DEFAULT:  .eabi_attribute 68, 3
 ; CORTEX-A12-DEFAULT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 20, 1
@@ -767,9 +771,6 @@
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 23, 3
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 24, 1
 ; CORTEX-A12-DEFAULT:  .eabi_attribute 25, 1
-; CORTEX-A12-DEFAULT:  .eabi_attribute 42, 1
-; CORTEX-A12-DEFAULT:  .eabi_attribute 44, 2
-; CORTEX-A12-DEFAULT:  .eabi_attribute 68, 3
 
 ; CORTEX-A12-DEFAULT-FAST-NOT:   .eabi_attribute 19
 ;; The A12 defaults to a VFPv3 FPU, so it flushes preserving the sign when
@@ -785,6 +786,9 @@
 ; CORTEX-A12-NOFPU:  .eabi_attribute 8, 1
 ; CORTEX-A12-NOFPU:  .eabi_attribute 9, 2
 ; CORTEX-A12-NOFPU-NOT:  .fpu
+; CORTEX-A12-NOFPU:  .eabi_attribute 42, 1
+; CORTEX-A12-NOFPU:  .eabi_attribute 44, 2
+; CORTEX-A12-NOFPU:  .eabi_attribute 68, 3
 ; CORTEX-A12-NOFPU-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A12-NOFPU:  .eabi_attribute 20, 1
@@ -793,9 +797,6 @@
 ; CORTEX-A12-NOFPU:  .eabi_attribute 23, 3
 ; CORTEX-A12-NOFPU:  .eabi_attribute 24, 1
 ; CORTEX-A12-NOFPU:  .eabi_attribute 25, 1
-; CORTEX-A12-NOFPU:  .eabi_attribute 42, 1
-; CORTEX-A12-NOFPU:  .eabi_attribute 44, 2
-; CORTEX-A12-NOFPU:  .eabi_attribute 68, 3
 
 ; CORTEX-A12-NOFPU-FAST-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
@@ -812,6 +813,11 @@
 ; CORTEX-A15: .eabi_attribute 8, 1
 ; CORTEX-A15: .eabi_attribute 9, 2
 ; CORTEX-A15: .fpu neon-vfpv4
+; CORTEX-A15-NOT: .eabi_attribute 27
+; CORTEX-A15: .eabi_attribute 36, 1
+; CORTEX-A15: .eabi_attribute 42, 1
+; CORTEX-A15: .eabi_attribute 44, 2
+; CORTEX-A15: .eabi_attribute 68, 3
 ; CORTEX-A15-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A15: .eabi_attribute 20, 1
@@ -820,13 +826,8 @@
 ; CORTEX-A15: .eabi_attribute 23, 3
 ; CORTEX-A15: .eabi_attribute 24, 1
 ; CORTEX-A15: .eabi_attribute 25, 1
-; CORTEX-A15-NOT: .eabi_attribute 27
 ; CORTEX-A15-NOT: .eabi_attribute 28
-; CORTEX-A15: .eabi_attribute 36, 1
 ; CORTEX-A15: .eabi_attribute 38, 1
-; CORTEX-A15: .eabi_attribute 42, 1
-; CORTEX-A15: .eabi_attribute 44, 2
-; CORTEX-A15: .eabi_attribute 68, 3
 
 ; CORTEX-A15-FAST-NOT:   .eabi_attribute 19
 ;; The A15 defaults to a VFPv3 FPU, so it flushes preserving the sign when
@@ -842,6 +843,9 @@
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 8, 1
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 9, 2
 ; CORTEX-A17-DEFAULT:  .fpu neon-vfpv4
+; CORTEX-A17-DEFAULT:  .eabi_attribute 42, 1
+; CORTEX-A17-DEFAULT:  .eabi_attribute 44, 2
+; CORTEX-A17-DEFAULT:  .eabi_attribute 68, 3
 ; CORTEX-A17-DEFAULT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 20, 1
@@ -850,9 +854,6 @@
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 23, 3
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 24, 1
 ; CORTEX-A17-DEFAULT:  .eabi_attribute 25, 1
-; CORTEX-A17-DEFAULT:  .eabi_attribute 42, 1
-; CORTEX-A17-DEFAULT:  .eabi_attribute 44, 2
-; CORTEX-A17-DEFAULT:  .eabi_attribute 68, 3
 
 ; CORTEX-A17-FAST-NOT:   .eabi_attribute 19
 ;; The A17 defaults to a VFPv3 FPU, so it flushes preserving the sign when
@@ -868,6 +869,9 @@
 ; CORTEX-A17-NOFPU:  .eabi_attribute 8, 1
 ; CORTEX-A17-NOFPU:  .eabi_attribute 9, 2
 ; CORTEX-A17-NOFPU-NOT:  .fpu
+; CORTEX-A17-NOFPU:  .eabi_attribute 42, 1
+; CORTEX-A17-NOFPU:  .eabi_attribute 44, 2
+; CORTEX-A17-NOFPU:  .eabi_attribute 68, 3
 ; CORTEX-A17-NOFPU-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A17-NOFPU:  .eabi_attribute 20, 1
@@ -876,9 +880,6 @@
 ; CORTEX-A17-NOFPU:  .eabi_attribute 23, 3
 ; CORTEX-A17-NOFPU:  .eabi_attribute 24, 1
 ; CORTEX-A17-NOFPU:  .eabi_attribute 25, 1
-; CORTEX-A17-NOFPU:  .eabi_attribute 42, 1
-; CORTEX-A17-NOFPU:  .eabi_attribute 44, 2
-; CORTEX-A17-NOFPU:  .eabi_attribute 68, 3
 
 ; CORTEX-A17-NOFPU-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
@@ -897,25 +898,25 @@
 
 ; CORTEX-M0:  .cpu cortex-m0
 ; CORTEX-M0:  .eabi_attribute 6, 12
-; CORTEX-M0-NOT:  .eabi_attribute 7
+; CORTEX-M0:  .eabi_attribute 7, 77
 ; CORTEX-M0:  .eabi_attribute 8, 0
 ; CORTEX-M0:  .eabi_attribute 9, 1
+; CORTEX-M0-NOT:  .eabi_attribute 27
+; CORTEX-M0-NOT:  .eabi_attribute 36
+; CORTEX-M0: .eabi_attribute 34, 0
+; CORTEX-M0-NOT:  .eabi_attribute 42
+; CORTEX-M0-NOT:  .eabi_attribute 44
+; CORTEX-M0-NOT:  .eabi_attribute 68
 ; CORTEX-M0-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M0:  .eabi_attribute 20, 1
 ; CORTEX-M0:  .eabi_attribute 21, 1
 ; CORTEX-M0-NOT:  .eabi_attribute 22
 ; CORTEX-M0:  .eabi_attribute 23, 3
-; CORTEX-M0: .eabi_attribute 34, 0
 ; CORTEX-M0:  .eabi_attribute 24, 1
 ; CORTEX-M0:  .eabi_attribute 25, 1
-; CORTEX-M0-NOT:  .eabi_attribute 27
 ; CORTEX-M0-NOT:  .eabi_attribute 28
-; CORTEX-M0-NOT:  .eabi_attribute 36
 ; CORTEX-M0:  .eabi_attribute 38, 1
-; CORTEX-M0-NOT:  .eabi_attribute 42
-; CORTEX-M0-NOT:  .eabi_attribute 44
-; CORTEX-M0-NOT:  .eabi_attribute 68
 
 ; CORTEX-M0-FAST-NOT:   .eabi_attribute 19
 ;; Despite the M0 CPU having no FPU in this scenario, we chose to
@@ -930,9 +931,14 @@
 
 ; CORTEX-M0PLUS:  .cpu cortex-m0plus
 ; CORTEX-M0PLUS:  .eabi_attribute 6, 12
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 7
+; CORTEX-M0PLUS:  .eabi_attribute 7, 77
 ; CORTEX-M0PLUS:  .eabi_attribute 8, 0
 ; CORTEX-M0PLUS:  .eabi_attribute 9, 1
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 27
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 36
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 42
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 44
+; CORTEX-M0PLUS-NOT:  .eabi_attribute 68
 ; CORTEX-M0PLUS-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M0PLUS:  .eabi_attribute 20, 1
@@ -941,13 +947,8 @@
 ; CORTEX-M0PLUS:  .eabi_attribute 23, 3
 ; CORTEX-M0PLUS:  .eabi_attribute 24, 1
 ; CORTEX-M0PLUS:  .eabi_attribute 25, 1
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 27
 ; CORTEX-M0PLUS-NOT:  .eabi_attribute 28
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 36
 ; CORTEX-M0PLUS:  .eabi_attribute 38, 1
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 42
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 44
-; CORTEX-M0PLUS-NOT:  .eabi_attribute 68
 
 ; CORTEX-M0PLUS-FAST-NOT:   .eabi_attribute 19
 ;; Despite the M0+ CPU having no FPU in this scenario, we chose to
@@ -962,9 +963,14 @@
 
 ; CORTEX-M1:  .cpu cortex-m1
 ; CORTEX-M1:  .eabi_attribute 6, 12
-; CORTEX-M1-NOT:  .eabi_attribute 7
+; CORTEX-M1:  .eabi_attribute 7, 77
 ; CORTEX-M1:  .eabi_attribute 8, 0
 ; CORTEX-M1:  .eabi_attribute 9, 1
+; CORTEX-M1-NOT:  .eabi_attribute 27
+; CORTEX-M1-NOT:  .eabi_attribute 36
+; CORTEX-M1-NOT:  .eabi_attribute 42
+; CORTEX-M1-NOT:  .eabi_attribute 44
+; CORTEX-M1-NOT:  .eabi_attribute 68
 ; CORTEX-M1-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M1:  .eabi_attribute 20, 1
@@ -973,13 +979,8 @@
 ; CORTEX-M1:  .eabi_attribute 23, 3
 ; CORTEX-M1:  .eabi_attribute 24, 1
 ; CORTEX-M1:  .eabi_attribute 25, 1
-; CORTEX-M1-NOT:  .eabi_attribute 27
 ; CORTEX-M1-NOT:  .eabi_attribute 28
-; CORTEX-M1-NOT:  .eabi_attribute 36
 ; CORTEX-M1:  .eabi_attribute 38, 1
-; CORTEX-M1-NOT:  .eabi_attribute 42
-; CORTEX-M1-NOT:  .eabi_attribute 44
-; CORTEX-M1-NOT:  .eabi_attribute 68
 
 ; CORTEX-M1-FAST-NOT:   .eabi_attribute 19
 ;; Despite the M1 CPU having no FPU in this scenario, we chose to
@@ -994,9 +995,13 @@
 
 ; SC000:  .cpu sc000
 ; SC000:  .eabi_attribute 6, 12
-; SC000-NOT:  .eabi_attribute 7
+; SC000:  .eabi_attribute 7, 77
 ; SC000:  .eabi_attribute 8, 0
 ; SC000:  .eabi_attribute 9, 1
+; SC000-NOT:  .eabi_attribute 27
+; SC000-NOT:  .eabi_attribute 42
+; SC000-NOT:  .eabi_attribute 44
+; SC000-NOT:  .eabi_attribute 68
 ; SC000-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; SC000:  .eabi_attribute 20, 1
@@ -1005,13 +1010,8 @@
 ; SC000:  .eabi_attribute 23, 3
 ; SC000:  .eabi_attribute 24, 1
 ; SC000:  .eabi_attribute 25, 1
-; SC000-NOT:  .eabi_attribute 27
 ; SC000-NOT:  .eabi_attribute 28
-; SC000-NOT:  .eabi_attribute 36
 ; SC000:  .eabi_attribute 38, 1
-; SC000-NOT:  .eabi_attribute 42
-; SC000-NOT:  .eabi_attribute 44
-; SC000-NOT:  .eabi_attribute 68
 
 ; SC000-FAST-NOT:   .eabi_attribute 19
 ;; Despite the SC000 CPU having no FPU in this scenario, we chose to
@@ -1029,6 +1029,11 @@
 ; CORTEX-M3:  .eabi_attribute 7, 77
 ; CORTEX-M3:  .eabi_attribute 8, 0
 ; CORTEX-M3:  .eabi_attribute 9, 2
+; CORTEX-M3-NOT:  .eabi_attribute 27
+; CORTEX-M3-NOT:  .eabi_attribute 36
+; CORTEX-M3-NOT:  .eabi_attribute 42
+; CORTEX-M3-NOT:  .eabi_attribute 44
+; CORTEX-M3-NOT:  .eabi_attribute 68
 ; CORTEX-M3-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M3:  .eabi_attribute 20, 1
@@ -1037,13 +1042,8 @@
 ; CORTEX-M3:  .eabi_attribute 23, 3
 ; CORTEX-M3:  .eabi_attribute 24, 1
 ; CORTEX-M3:  .eabi_attribute 25, 1
-; CORTEX-M3-NOT:  .eabi_attribute 27
 ; CORTEX-M3-NOT:  .eabi_attribute 28
-; CORTEX-M3-NOT:  .eabi_attribute 36
 ; CORTEX-M3:  .eabi_attribute 38, 1
-; CORTEX-M3-NOT:  .eabi_attribute 42
-; CORTEX-M3-NOT:  .eabi_attribute 44
-; CORTEX-M3-NOT:  .eabi_attribute 68
 
 ; CORTEX-M3-FAST-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
@@ -1059,6 +1059,11 @@
 ; SC300:  .eabi_attribute 7, 77
 ; SC300:  .eabi_attribute 8, 0
 ; SC300:  .eabi_attribute 9, 2
+; SC300-NOT:  .eabi_attribute 27
+; SC300-NOT:  .eabi_attribute 36
+; SC300-NOT:  .eabi_attribute 42
+; SC300-NOT:  .eabi_attribute 44
+; SC300-NOT:  .eabi_attribute 68
 ; SC300-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; SC300:  .eabi_attribute 20, 1
@@ -1067,13 +1072,8 @@
 ; SC300:  .eabi_attribute 23, 3
 ; SC300:  .eabi_attribute 24, 1
 ; SC300:  .eabi_attribute 25, 1
-; SC300-NOT:  .eabi_attribute 27
 ; SC300-NOT:  .eabi_attribute 28
-; SC300-NOT:  .eabi_attribute 36
 ; SC300:  .eabi_attribute 38, 1
-; SC300-NOT:  .eabi_attribute 42
-; SC300-NOT:  .eabi_attribute 44
-; SC300-NOT:  .eabi_attribute 68
 
 ; SC300-FAST-NOT:   .eabi_attribute 19
 ;; Despite there being no FPU, we chose to flush to zero preserving
@@ -1090,6 +1090,11 @@
 ; CORTEX-M4-SOFT:  .eabi_attribute 8, 0
 ; CORTEX-M4-SOFT:  .eabi_attribute 9, 2
 ; CORTEX-M4-SOFT:  .fpu fpv4-sp-d16
+; CORTEX-M4-SOFT:  .eabi_attribute 27, 1
+; CORTEX-M4-SOFT:  .eabi_attribute 36, 1
+; CORTEX-M4-SOFT-NOT:  .eabi_attribute 42
+; CORTEX-M4-SOFT-NOT:  .eabi_attribute 44
+; CORTEX-M4-SOFT-NOT:  .eabi_attribute 68
 ; CORTEX-M4-SOFT-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M4-SOFT:  .eabi_attribute 20, 1
@@ -1098,13 +1103,8 @@
 ; CORTEX-M4-SOFT:  .eabi_attribute 23, 3
 ; CORTEX-M4-SOFT:  .eabi_attribute 24, 1
 ; CORTEX-M4-SOFT:  .eabi_attribute 25, 1
-; CORTEX-M4-SOFT:  .eabi_attribute 27, 1
 ; CORTEX-M4-SOFT-NOT:  .eabi_attribute 28
-; CORTEX-M4-SOFT:  .eabi_attribute 36, 1
 ; CORTEX-M4-SOFT:  .eabi_attribute 38, 1
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 42
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 44
-; CORTEX-M4-SOFT-NOT:  .eabi_attribute 68
 
 ; CORTEX-M4-SOFT-FAST-NOT:   .eabi_attribute 19
 ;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
@@ -1120,6 +1120,11 @@
 ; CORTEX-M4-HARD:  .eabi_attribute 8, 0
 ; CORTEX-M4-HARD:  .eabi_attribute 9, 2
 ; CORTEX-M4-HARD:  .fpu fpv4-sp-d16
+; CORTEX-M4-HARD:  .eabi_attribute 27, 1
+; CORTEX-M4-HARD:  .eabi_attribute 36, 1
+; CORTEX-M4-HARD-NOT:  .eabi_attribute 42
+; CORTEX-M4-HARD-NOT:  .eabi_attribute 44
+; CORTEX-M4-HARD-NOT:  .eabi_attribute 68
 ; CORTEX-M4-HARD-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-M4-HARD:  .eabi_attribute 20, 1
@@ -1128,13 +1133,8 @@
 ; CORTEX-M4-HARD:  .eabi_attribute 23, 3
 ; CORTEX-M4-HARD:  .eabi_attribute 24, 1
 ; CORTEX-M4-HARD:  .eabi_attribute 25, 1
-; CORTEX-M4-HARD:  .eabi_attribute 27, 1
 ; CORTEX-M4-HARD:  .eabi_attribute 28, 1
-; CORTEX-M4-HARD:  .eabi_attribute 36, 1
 ; CORTEX-M4-HARD:  .eabi_attribute 38, 1
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 42
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 44
-; CORTEX-M4-HARD-NOT:  .eabi_attribute 68
 
 ; CORTEX-M4-HARD-FAST-NOT:   .eabi_attribute 19
 ;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
@@ -1152,6 +1152,11 @@
 ; CORTEX-M7-SOFT-NOT: .fpu
 ; CORTEX-M7-SINGLE:  .fpu fpv5-sp-d16
 ; CORTEX-M7-DOUBLE:  .fpu fpv5-d16
+; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
+; CORTEX-M7-SINGLE:  .eabi_attribute 27, 1
+; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
+; CORTEX-M7:  .eabi_attribute 36, 1
+; CORTEX-M7-NOT:  .eabi_attribute 44
 ; CORTEX-M7:  .eabi_attribute 17, 1
 ; CORTEX-M7-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
@@ -1161,12 +1166,7 @@
 ; CORTEX-M7:  .eabi_attribute 23, 3
 ; CORTEX-M7:  .eabi_attribute 24, 1
 ; CORTEX-M7:  .eabi_attribute 25, 1
-; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
-; CORTEX-M7-SINGLE:  .eabi_attribute 27, 1
-; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
-; CORTEX-M7:  .eabi_attribute 36, 1
 ; CORTEX-M7:  .eabi_attribute 38, 1
-; CORTEX-M7-NOT:  .eabi_attribute 44
 ; CORTEX-M7:  .eabi_attribute 14, 0
 
 ; CORTEX-M7-NOFPU-FAST-NOT:   .eabi_attribute 19
@@ -1186,6 +1186,10 @@
 ; CORTEX-R4:  .eabi_attribute 8, 1
 ; CORTEX-R4:  .eabi_attribute 9, 2
 ; CORTEX-R4-NOT:  .fpu vfpv3-d16
+; CORTEX-R4-NOT:  .eabi_attribute 36
+; CORTEX-R4-NOT:  .eabi_attribute 42
+; CORTEX-R4-NOT:  .eabi_attribute 44
+; CORTEX-R4-NOT:  .eabi_attribute 68
 ; CORTEX-R4-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R4:  .eabi_attribute 20, 1
@@ -1195,11 +1199,7 @@
 ; CORTEX-R4:  .eabi_attribute 24, 1
 ; CORTEX-R4:  .eabi_attribute 25, 1
 ; CORTEX-R4-NOT:  .eabi_attribute 28
-; CORTEX-R4-NOT:  .eabi_attribute 36
 ; CORTEX-R4:  .eabi_attribute 38, 1
-; CORTEX-R4-NOT:  .eabi_attribute 42
-; CORTEX-R4-NOT:  .eabi_attribute 44
-; CORTEX-R4-NOT:  .eabi_attribute 68
 
 ; CORTEX-R4F:  .cpu cortex-r4f
 ; CORTEX-R4F:  .eabi_attribute 6, 10
@@ -1207,6 +1207,11 @@
 ; CORTEX-R4F:  .eabi_attribute 8, 1
 ; CORTEX-R4F:  .eabi_attribute 9, 2
 ; CORTEX-R4F:  .fpu vfpv3-d16
+; CORTEX-R4F-NOT:  .eabi_attribute 27, 1
+; CORTEX-R4F-NOT:  .eabi_attribute 36
+; CORTEX-R4F-NOT:  .eabi_attribute 42
+; CORTEX-R4F-NOT:  .eabi_attribute 44
+; CORTEX-R4F-NOT:  .eabi_attribute 68
 ; CORTEX-R4F-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R4F:  .eabi_attribute 20, 1
@@ -1215,13 +1220,8 @@
 ; CORTEX-R4F:  .eabi_attribute 23, 3
 ; CORTEX-R4F:  .eabi_attribute 24, 1
 ; CORTEX-R4F:  .eabi_attribute 25, 1
-; CORTEX-R4F-NOT:  .eabi_attribute 27, 1
 ; CORTEX-R4F-NOT:  .eabi_attribute 28
-; CORTEX-R4F-NOT:  .eabi_attribute 36
 ; CORTEX-R4F:  .eabi_attribute 38, 1
-; CORTEX-R4F-NOT:  .eabi_attribute 42
-; CORTEX-R4F-NOT:  .eabi_attribute 44
-; CORTEX-R4F-NOT:  .eabi_attribute 68
 
 ; CORTEX-R5:  .cpu cortex-r5
 ; CORTEX-R5:  .eabi_attribute 6, 10
@@ -1229,6 +1229,11 @@
 ; CORTEX-R5:  .eabi_attribute 8, 1
 ; CORTEX-R5:  .eabi_attribute 9, 2
 ; CORTEX-R5:  .fpu vfpv3-d16
+; CORTEX-R5-NOT:  .eabi_attribute 27, 1
+; CORTEX-R5-NOT:  .eabi_attribute 36
+; CORTEX-R5:  .eabi_attribute 44, 2
+; CORTEX-R5-NOT:  .eabi_attribute 42
+; CORTEX-R5-NOT:  .eabi_attribute 68
 ; CORTEX-R5-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R5:  .eabi_attribute 20, 1
@@ -1237,13 +1242,8 @@
 ; CORTEX-R5:  .eabi_attribute 23, 3
 ; CORTEX-R5:  .eabi_attribute 24, 1
 ; CORTEX-R5:  .eabi_attribute 25, 1
-; CORTEX-R5-NOT:  .eabi_attribute 27, 1
 ; CORTEX-R5-NOT:  .eabi_attribute 28
-; CORTEX-R5-NOT:  .eabi_attribute 36
 ; CORTEX-R5:  .eabi_attribute 38, 1
-; CORTEX-R5-NOT:  .eabi_attribute 42
-; CORTEX-R5:  .eabi_attribute 44, 2
-; CORTEX-R5-NOT:  .eabi_attribute 68
 
 ; CORTEX-R5-FAST-NOT:   .eabi_attribute 19
 ;; The R5 has the VFPv3 FP unit, which always flushes preserving sign.
@@ -1258,6 +1258,10 @@
 ; CORTEX-R7:  .eabi_attribute 8, 1
 ; CORTEX-R7:  .eabi_attribute 9, 2
 ; CORTEX-R7:  .fpu vfpv3-d16-fp16
+; CORTEX-R7:  .eabi_attribute 36, 1
+; CORTEX-R7:  .eabi_attribute 42, 1
+; CORTEX-R7:  .eabi_attribute 44, 2
+; CORTEX-R7-NOT:  .eabi_attribute 68
 ; CORTEX-R7-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R7:  .eabi_attribute 20, 1
@@ -1267,11 +1271,7 @@
 ; CORTEX-R7:  .eabi_attribute 24, 1
 ; CORTEX-R7:  .eabi_attribute 25, 1
 ; CORTEX-R7-NOT:  .eabi_attribute 28
-; CORTEX-R7:  .eabi_attribute 36, 1
 ; CORTEX-R7:  .eabi_attribute 38, 1
-; CORTEX-R7:  .eabi_attribute 42, 1
-; CORTEX-R7:  .eabi_attribute 44, 2
-; CORTEX-R7-NOT:  .eabi_attribute 68
 
 ; CORTEX-R7-FAST-NOT:   .eabi_attribute 19
 ;; The R7 has the VFPv3 FP unit, which always flushes preserving sign.
@@ -1286,6 +1286,10 @@
 ; CORTEX-R8:  .eabi_attribute 8, 1
 ; CORTEX-R8:  .eabi_attribute 9, 2
 ; CORTEX-R8:  .fpu vfpv3-d16-fp16
+; CORTEX-R8:  .eabi_attribute 36, 1
+; CORTEX-R8:  .eabi_attribute 42, 1
+; CORTEX-R8:  .eabi_attribute 44, 2
+; CORTEX-R8-NOT:  .eabi_attribute 68
 ; CORTEX-R8-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R8:  .eabi_attribute 20, 1
@@ -1295,11 +1299,7 @@
 ; CORTEX-R8:  .eabi_attribute 24, 1
 ; CORTEX-R8:  .eabi_attribute 25, 1
 ; CORTEX-R8-NOT:  .eabi_attribute 28
-; CORTEX-R8:  .eabi_attribute 36, 1
 ; CORTEX-R8:  .eabi_attribute 38, 1
-; CORTEX-R8:  .eabi_attribute 42, 1
-; CORTEX-R8:  .eabi_attribute 44, 2
-; CORTEX-R8-NOT:  .eabi_attribute 68
 
 ; CORTEX-R8-FAST-NOT:   .eabi_attribute 19
 ;; The R8 has the VFPv3 FP unit, which always flushes preserving sign.
@@ -1315,6 +1315,11 @@
 ; CORTEX-A32:  .eabi_attribute 9, 2
 ; CORTEX-A32:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A32:  .eabi_attribute 12, 3
+; CORTEX-A32-NOT:  .eabi_attribute 27
+; CORTEX-A32:  .eabi_attribute 36, 1
+; CORTEX-A32:  .eabi_attribute 42, 1
+; CORTEX-A32-NOT:  .eabi_attribute 44
+; CORTEX-A32:  .eabi_attribute 68, 3
 ; CORTEX-A32-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A32:  .eabi_attribute 20, 1
@@ -1323,13 +1328,8 @@
 ; CORTEX-A32:  .eabi_attribute 23, 3
 ; CORTEX-A32:  .eabi_attribute 24, 1
 ; CORTEX-A32:  .eabi_attribute 25, 1
-; CORTEX-A32-NOT:  .eabi_attribute 27
 ; CORTEX-A32-NOT:  .eabi_attribute 28
-; CORTEX-A32:  .eabi_attribute 36, 1
 ; CORTEX-A32:  .eabi_attribute 38, 1
-; CORTEX-A32:  .eabi_attribute 42, 1
-; CORTEX-A32-NOT:  .eabi_attribute 44
-; CORTEX-A32:  .eabi_attribute 68, 3
 
 ; CORTEX-A32-FAST-NOT:   .eabi_attribute 19
 ;; The A32 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1343,20 +1343,20 @@
 ; CORTEX-M23:  .eabi_attribute 7, 77
 ; CORTEX-M23:  .eabi_attribute 8, 0
 ; CORTEX-M23:  .eabi_attribute 9, 3
+; CORTEX-M23-NOT:  .eabi_attribute 27
+; CORTEX-M23:  .eabi_attribute 34, 1
+; CORTEX-M23-NOT:  .eabi_attribute 44
 ; CORTEX-M23:  .eabi_attribute 17, 1
 ;; We default to IEEE 754 compliance
 ; CORTEX-M23-NOT:   .eabi_attribute 19
 ; CORTEX-M23:  .eabi_attribute 20, 1
 ; CORTEX-M23:  .eabi_attribute 21, 1
 ; CORTEX-M23:  .eabi_attribute 23, 3
-; CORTEX-M23:  .eabi_attribute 34, 1
 ; CORTEX-M23:  .eabi_attribute 24, 1
-; CORTEX-M23-NOT:  .eabi_attribute 27
 ; CORTEX-M23-NOT:  .eabi_attribute 28
 ; CORTEX-M23:  .eabi_attribute 25, 1
 ; CORTEX-M23:  .eabi_attribute 38, 1
 ; CORTEX-M23:  .eabi_attribute 14, 0
-; CORTEX-M23-NOT:  .eabi_attribute 44
 
 ; CORTEX-M33:  .cpu cortex-m33
 ; CORTEX-M33:  .eabi_attribute 6, 17
@@ -1364,21 +1364,21 @@
 ; CORTEX-M33:  .eabi_attribute 8, 0
 ; CORTEX-M33:  .eabi_attribute 9, 3
 ; CORTEX-M33:  .fpu fpv5-sp-d16
+; CORTEX-M33:  .eabi_attribute 27, 1
+; CORTEX-M33:  .eabi_attribute 36, 1
+; CORTEX-M33-NOT:  .eabi_attribute 44
+; CORTEX-M33:  .eabi_attribute 46, 1
+; CORTEX-M33:  .eabi_attribute 34, 1
 ; CORTEX-M33:  .eabi_attribute 17, 1
 ;; We default to IEEE 754 compliance
 ; CORTEX-M23-NOT:   .eabi_attribute 19
 ; CORTEX-M33:  .eabi_attribute 20, 1
 ; CORTEX-M33:  .eabi_attribute 21, 1
 ; CORTEX-M33:  .eabi_attribute 23, 3
-; CORTEX-M33:  .eabi_attribute 34, 1
 ; CORTEX-M33:  .eabi_attribute 24, 1
 ; CORTEX-M33:  .eabi_attribute 25, 1
-; CORTEX-M33:  .eabi_attribute 27, 1
 ; CORTEX-M33-NOT:  .eabi_attribute 28
-; CORTEX-M33:  .eabi_attribute 36, 1
 ; CORTEX-M33:  .eabi_attribute 38, 1
-; CORTEX-M33:  .eabi_attribute 46, 1
-; CORTEX-M33-NOT:  .eabi_attribute 44
 ; CORTEX-M33:  .eabi_attribute 14, 0
 
 ; CORTEX-M33-FAST-NOT:   .eabi_attribute 19
@@ -1394,6 +1394,11 @@
 ; CORTEX-A35:  .eabi_attribute 9, 2
 ; CORTEX-A35:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A35:  .eabi_attribute 12, 3
+; CORTEX-A35-NOT:  .eabi_attribute 27
+; CORTEX-A35:  .eabi_attribute 36, 1
+; CORTEX-A35:  .eabi_attribute 42, 1
+; CORTEX-A35-NOT:  .eabi_attribute 44
+; CORTEX-A35:  .eabi_attribute 68, 3
 ; CORTEX-A35-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A35:  .eabi_attribute 20, 1
@@ -1402,13 +1407,8 @@
 ; CORTEX-A35:  .eabi_attribute 23, 3
 ; CORTEX-A35:  .eabi_attribute 24, 1
 ; CORTEX-A35:  .eabi_attribute 25, 1
-; CORTEX-A35-NOT:  .eabi_attribute 27
 ; CORTEX-A35-NOT:  .eabi_attribute 28
-; CORTEX-A35:  .eabi_attribute 36, 1
 ; CORTEX-A35:  .eabi_attribute 38, 1
-; CORTEX-A35:  .eabi_attribute 42, 1
-; CORTEX-A35-NOT:  .eabi_attribute 44
-; CORTEX-A35:  .eabi_attribute 68, 3
 
 ; CORTEX-A35-FAST-NOT:   .eabi_attribute 19
 ;; The A35 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1424,6 +1424,11 @@
 ; CORTEX-A53:  .eabi_attribute 9, 2
 ; CORTEX-A53:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A53:  .eabi_attribute 12, 3
+; CORTEX-A53-NOT:  .eabi_attribute 27
+; CORTEX-A53:  .eabi_attribute 36, 1
+; CORTEX-A53:  .eabi_attribute 42, 1
+; CORTEX-A53-NOT:  .eabi_attribute 44
+; CORTEX-A53:  .eabi_attribute 68, 3
 ; CORTEX-A53-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A53:  .eabi_attribute 20, 1
@@ -1432,13 +1437,8 @@
 ; CORTEX-A53:  .eabi_attribute 23, 3
 ; CORTEX-A53:  .eabi_attribute 24, 1
 ; CORTEX-A53:  .eabi_attribute 25, 1
-; CORTEX-A53-NOT:  .eabi_attribute 27
 ; CORTEX-A53-NOT:  .eabi_attribute 28
-; CORTEX-A53:  .eabi_attribute 36, 1
 ; CORTEX-A53:  .eabi_attribute 38, 1
-; CORTEX-A53:  .eabi_attribute 42, 1
-; CORTEX-A53-NOT:  .eabi_attribute 44
-; CORTEX-A53:  .eabi_attribute 68, 3
 
 ; CORTEX-A53-FAST-NOT:   .eabi_attribute 19
 ;; The A53 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1454,6 +1454,11 @@
 ; CORTEX-A57:  .eabi_attribute 9, 2
 ; CORTEX-A57:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A57:  .eabi_attribute 12, 3
+; CORTEX-A57-NOT:  .eabi_attribute 27
+; CORTEX-A57:  .eabi_attribute 36, 1
+; CORTEX-A57:  .eabi_attribute 42, 1
+; CORTEX-A57-NOT:  .eabi_attribute 44
+; CORTEX-A57:  .eabi_attribute 68, 3
 ; CORTEX-A57-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A57:  .eabi_attribute 20, 1
@@ -1462,13 +1467,8 @@
 ; CORTEX-A57:  .eabi_attribute 23, 3
 ; CORTEX-A57:  .eabi_attribute 24, 1
 ; CORTEX-A57:  .eabi_attribute 25, 1
-; CORTEX-A57-NOT:  .eabi_attribute 27
 ; CORTEX-A57-NOT:  .eabi_attribute 28
-; CORTEX-A57:  .eabi_attribute 36, 1
 ; CORTEX-A57:  .eabi_attribute 38, 1
-; CORTEX-A57:  .eabi_attribute 42, 1
-; CORTEX-A57-NOT:  .eabi_attribute 44
-; CORTEX-A57:  .eabi_attribute 68, 3
 
 ; CORTEX-A57-FAST-NOT:   .eabi_attribute 19
 ;; The A57 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1484,6 +1484,11 @@
 ; CORTEX-A72:  .eabi_attribute 9, 2
 ; CORTEX-A72:  .fpu crypto-neon-fp-armv8
 ; CORTEX-A72:  .eabi_attribute 12, 3
+; CORTEX-A72-NOT:  .eabi_attribute 27
+; CORTEX-A72:  .eabi_attribute 36, 1
+; CORTEX-A72:  .eabi_attribute 42, 1
+; CORTEX-A72-NOT:  .eabi_attribute 44
+; CORTEX-A72:  .eabi_attribute 68, 3
 ; CORTEX-A72-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A72:  .eabi_attribute 20, 1
@@ -1492,13 +1497,8 @@
 ; CORTEX-A72:  .eabi_attribute 23, 3
 ; CORTEX-A72:  .eabi_attribute 24, 1
 ; CORTEX-A72:  .eabi_attribute 25, 1
-; CORTEX-A72-NOT:  .eabi_attribute 27
 ; CORTEX-A72-NOT:  .eabi_attribute 28
-; CORTEX-A72:  .eabi_attribute 36, 1
 ; CORTEX-A72:  .eabi_attribute 38, 1
-; CORTEX-A72:  .eabi_attribute 42, 1
-; CORTEX-A72-NOT:  .eabi_attribute 44
-; CORTEX-A72:  .eabi_attribute 68, 3
 
 ; CORTEX-A72-FAST-NOT:   .eabi_attribute 19
 ;; The A72 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1514,6 +1514,11 @@
 ; CORTEX-A73:  .eabi_attribute 9, 2
 ; CORTEX-A73:  .fpu  crypto-neon-fp-armv8
 ; CORTEX-A73:  .eabi_attribute 12, 3
+; CORTEX-A73-NOT: .eabi_attribute 27
+; CORTEX-A73:  .eabi_attribute 36, 1
+; CORTEX-A73:  .eabi_attribute 42, 1
+; CORTEX-A73-NOT: .eabi_attribute 44
+; CORTEX-A73:  .eabi_attribute 68, 3
 ; CORTEX-A73-NOT: .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-A73:  .eabi_attribute 20, 1
@@ -1522,14 +1527,9 @@
 ; CORTEX-A73:  .eabi_attribute 23, 3
 ; CORTEX-A73:  .eabi_attribute 24, 1
 ; CORTEX-A73:  .eabi_attribute 25, 1
-; CORTEX-A73-NOT: .eabi_attribute 27
 ; CORTEX-A73-NOT: .eabi_attribute 28
-; CORTEX-A73:  .eabi_attribute 36, 1
 ; CORTEX-A73:  .eabi_attribute 38, 1
-; CORTEX-A73:  .eabi_attribute 42, 1
-; CORTEX-A73-NOT: .eabi_attribute 44
 ; CORTEX-A73:  .eabi_attribute 14, 0
-; CORTEX-A73:  .eabi_attribute 68, 3
 
 ; EXYNOS-M1:  .cpu exynos-m1
 ; EXYNOS-M1:  .eabi_attribute 6, 14
@@ -1538,6 +1538,11 @@
 ; EXYNOS-M1:  .eabi_attribute 9, 2
 ; EXYNOS-M1:  .fpu crypto-neon-fp-armv8
 ; EXYNOS-M1:  .eabi_attribute 12, 3
+; EXYNOS-M1-NOT:  .eabi_attribute 27
+; EXYNOS-M1:  .eabi_attribute 36, 1
+; EXYNOS-M1:  .eabi_attribute 42, 1
+; EXYNOS-M1-NOT:  .eabi_attribute 44
+; EXYNOS-M1:  .eabi_attribute 68, 3
 ; EXYNOS-M1-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; EXYNOS-M1:  .eabi_attribute 20, 1
@@ -1546,13 +1551,8 @@
 ; EXYNOS-M1:  .eabi_attribute 23, 3
 ; EXYNOS-M1:  .eabi_attribute 24, 1
 ; EXYNOS-M1:  .eabi_attribute 25, 1
-; EXYNOS-M1-NOT:  .eabi_attribute 27
 ; EXYNOS-M1-NOT:  .eabi_attribute 28
-; EXYNOS-M1:  .eabi_attribute 36, 1
 ; EXYNOS-M1:  .eabi_attribute 38, 1
-; EXYNOS-M1:  .eabi_attribute 42, 1
-; EXYNOS-M1-NOT:  .eabi_attribute 44
-; EXYNOS-M1:  .eabi_attribute 68, 3
 
 ; EXYNOS-M1-FAST-NOT:   .eabi_attribute 19
 ;; The exynos-m1 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1568,6 +1568,11 @@
 ; EXYNOS-M2:  .eabi_attribute 9, 2
 ; EXYNOS-M2:  .fpu crypto-neon-fp-armv8
 ; EXYNOS-M2:  .eabi_attribute 12, 3
+; EXYNOS-M2-NOT:  .eabi_attribute 27
+; EXYNOS-M2:  .eabi_attribute 36, 1
+; EXYNOS-M2:  .eabi_attribute 42, 1
+; EXYNOS-M2-NOT:  .eabi_attribute 44
+; EXYNOS-M2:  .eabi_attribute 68, 3
 ; EXYNOS-M2-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; EXYNOS-M2:  .eabi_attribute 20, 1
@@ -1576,13 +1581,8 @@
 ; EXYNOS-M2:  .eabi_attribute 23, 3
 ; EXYNOS-M2:  .eabi_attribute 24, 1
 ; EXYNOS-M2:  .eabi_attribute 25, 1
-; EXYNOS-M2-NOT:  .eabi_attribute 27
 ; EXYNOS-M2-NOT:  .eabi_attribute 28
-; EXYNOS-M2:  .eabi_attribute 36, 1
 ; EXYNOS-M2:  .eabi_attribute 38, 1
-; EXYNOS-M2:  .eabi_attribute 42, 1
-; EXYNOS-M2-NOT:  .eabi_attribute 44
-; EXYNOS-M2:  .eabi_attribute 68, 3
 
 ; EXYNOS-M3:  .cpu exynos-m3
 ; EXYNOS-M3:  .eabi_attribute 6, 14
@@ -1591,6 +1591,11 @@
 ; EXYNOS-M3:  .eabi_attribute 9, 2
 ; EXYNOS-M3:  .fpu crypto-neon-fp-armv8
 ; EXYNOS-M3:  .eabi_attribute 12, 3
+; EXYNOS-M3-NOT:  .eabi_attribute 27
+; EXYNOS-M3:  .eabi_attribute 36, 1
+; EXYNOS-M3:  .eabi_attribute 42, 1
+; EXYNOS-M3-NOT:  .eabi_attribute 44
+; EXYNOS-M3:  .eabi_attribute 68, 3
 ; EXYNOS-M3-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; EXYNOS-M3:  .eabi_attribute 20, 1
@@ -1599,13 +1604,8 @@
 ; EXYNOS-M3:  .eabi_attribute 23, 3
 ; EXYNOS-M3:  .eabi_attribute 24, 1
 ; EXYNOS-M3:  .eabi_attribute 25, 1
-; EXYNOS-M3-NOT:  .eabi_attribute 27
 ; EXYNOS-M3-NOT:  .eabi_attribute 28
-; EXYNOS-M3:  .eabi_attribute 36, 1
 ; EXYNOS-M3:  .eabi_attribute 38, 1
-; EXYNOS-M3:  .eabi_attribute 42, 1
-; EXYNOS-M3-NOT:  .eabi_attribute 44
-; EXYNOS-M3:  .eabi_attribute 68, 3
 
 ; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16
 ; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16
@@ -1619,6 +1619,11 @@
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 9, 2
 ; GENERIC-ARMV8_1-A:  .fpu crypto-neon-fp-armv8
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 12, 4
+; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 27
+; GENERIC-ARMV8_1-A:  .eabi_attribute 36, 1
+; GENERIC-ARMV8_1-A:  .eabi_attribute 42, 1
+; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 44
+; GENERIC-ARMV8_1-A:  .eabi_attribute 68, 3
 ; GENERIC-ARMV8_1-A-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 20, 1
@@ -1627,13 +1632,8 @@
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 23, 3
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 24, 1
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 25, 1
-; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 27
 ; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 28
-; GENERIC-ARMV8_1-A:  .eabi_attribute 36, 1
 ; GENERIC-ARMV8_1-A:  .eabi_attribute 38, 1
-; GENERIC-ARMV8_1-A:  .eabi_attribute 42, 1
-; GENERIC-ARMV8_1-A-NOT:  .eabi_attribute 44
-; GENERIC-ARMV8_1-A:  .eabi_attribute 68, 3
 
 ; GENERIC-ARMV8_1-A-FAST-NOT:   .eabi_attribute 19
 ;; GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1670,23 +1670,16 @@
 ; ARMv8R-SP-NOT: .eabi_attribute 12
 ; ARMv8R-NEON: .fpu    neon-fp-armv8
 ; ARMv8R-NEON: .eabi_attribute 12, 3   @ Tag_Advanced_SIMD_arch
-; ARMv8R: .eabi_attribute 17, 1   @ Tag_ABI_PCS_GOT_use
-; ARMv8R: .eabi_attribute 20, 1   @ Tag_ABI_FP_denormal
-; ARMv8R: .eabi_attribute 21, 1   @ Tag_ABI_FP_exceptions
-; ARMv8R: .eabi_attribute 23, 3   @ Tag_ABI_FP_number_model
-; ARMv8R: .eabi_attribute 34, 1   @ Tag_CPU_unaligned_access
-; ARMv8R: .eabi_attribute 24, 1   @ Tag_ABI_align_needed
-; ARMv8R: .eabi_attribute 25, 1   @ Tag_ABI_align_preserved
 ; ARMv8R-NOFPU-NOT: .eabi_attribute 27
 ; ARMv8R-SP: .eabi_attribute 27, 1   @ Tag_ABI_HardFP_use
 ; ARMv8R-NEON-NOT: .eabi_attribute 27
 ; ARMv8R-NOFPU-NOT: .eabi_attribute 36
 ; ARMv8R-SP: .eabi_attribute 36, 1   @ Tag_FP_HP_extension
 ; ARMv8R-NEON: .eabi_attribute 36, 1   @ Tag_FP_HP_extension
-; ARMv8R: .eabi_attribute 38, 1   @ Tag_ABI_FP_16bit_format
 ; ARMv8R: .eabi_attribute 42, 1   @ Tag_MPextension_use
-; ARMv8R: .eabi_attribute 14, 0   @ Tag_ABI_PCS_R9_use
 ; ARMv8R: .eabi_attribute 68, 2   @ Tag_Virtualization_use
+; ARMv8R: .eabi_attribute 38, 1   @ Tag_ABI_FP_16bit_format
+; ARMv8R: .eabi_attribute 14, 0   @ Tag_ABI_PCS_R9_use
 
 define i32 @f(i64 %z) {
     ret i32 0