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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/ARM/big-endian-neon-extend.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/ARM/big-endian-neon-extend.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/big-endian-neon-extend.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll b/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll index 1498356eb97..1e35305bdba 100644 --- a/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll +++ b/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll @@ -14,7 +14,7 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr - %1 = load <2 x i8>* %loadaddr + %1 = load <2 x i8>, <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i64> store <2 x i64> %2, <2 x i64>* %storeaddr ret void @@ -33,7 +33,7 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr - %1 = load <2 x i16>* %loadaddr + %1 = load <2 x i16>, <2 x i16>* %loadaddr %2 = zext <2 x i16> %1 to <2 x i64> store <2 x i64> %2, <2 x i64>* %storeaddr ret void @@ -49,7 +49,7 @@ define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]] ; CHECK-NEXT: vstr [[REG]], [r1] ; CHECK-NEXT: bx lr - %1 = load <2 x i8>* %loadaddr + %1 = load <2 x i8>, <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i32> store <2 x i32> %2, <2 x i32>* %storeaddr ret void @@ -63,7 +63,7 @@ define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeadd ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]] ; CHECK-NEXT: vstr [[REG]], [r1] ; CHECK-NEXT: bx lr - %1 = load <2 x i16>* %loadaddr + %1 = load <2 x i16>, <2 x i16>* %loadaddr %2 = zext <2 x i16> %1 to <2 x i32> store <2 x i32> %2, <2 x i32>* %storeaddr ret void @@ -80,7 +80,7 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}} ; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32] ; CHECK-NEXT: bx lr - %1 = load <2 x i8>* %loadaddr + %1 = load <2 x i8>, <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i16> store <2 x i16> %2, <2 x i16>* %storeaddr ret void @@ -95,7 +95,7 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] ; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] ; CHECK-NEXT: bx lr - %1 = load <4 x i8>* %loadaddr + %1 = load <4 x i8>, <4 x i8>* %loadaddr %2 = zext <4 x i8> %1 to <4 x i32> store <4 x i32> %2, <4 x i32>* %storeaddr ret void @@ -109,7 +109,7 @@ define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ; CHECK-NEXT: vrev64.16 [[REG]], [[REG]] ; CHECK-NEXT: vstr [[REG]], [r1] ; CHECK-NEXT: bx lr - %1 = load <4 x i8>* %loadaddr + %1 = load <4 x i8>, <4 x i8>* %loadaddr %2 = zext <4 x i8> %1 to <4 x i16> store <4 x i16> %2, <4 x i16>* %storeaddr ret void |
