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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-31 02:08:34 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-31 02:08:34 +0000 |
| commit | d3bda3c5b9b28ac156a731c26e790d27faf3a338 (patch) | |
| tree | 68faf81b2b520f68d30eb78745cf52b0f22b85ee /llvm/test/CodeGen/ARM/atomic-op.ll | |
| parent | c769722a16587a09fdc183b45d952f43d02dee69 (diff) | |
| download | bcm5719-llvm-d3bda3c5b9b28ac156a731c26e790d27faf3a338.tar.gz bcm5719-llvm-d3bda3c5b9b28ac156a731c26e790d27faf3a338.zip | |
Fix a couple of typos in EmitAtomic.
Thumb2 instructions are mostly constrained to rGPR, not tGPR which is
for Thumb1.
rdar://problem/12203728
llvm-svn: 162968
Diffstat (limited to 'llvm/test/CodeGen/ARM/atomic-op.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-op.ll | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/atomic-op.ll b/llvm/test/CodeGen/ARM/atomic-op.ll index 8967730835a..6e6b36377fd 100644 --- a/llvm/test/CodeGen/ARM/atomic-op.ll +++ b/llvm/test/CodeGen/ARM/atomic-op.ll @@ -159,3 +159,13 @@ entry: store i8 %3, i8* %old ret void } + +; CHECK: func4 +; This function should not need to use callee-saved registers. +; rdar://problem/12203728 +; CHECK-NOT: r4 +define i32 @func4(i32* %p) nounwind optsize ssp { +entry: + %0 = atomicrmw add i32* %p, i32 1 monotonic + ret i32 %0 +} |
