[ARM/AArch64] Relocate and update InterleavedAccessPass tests (NFC)

The interleaved access pass is an IR-to-IR transformation that runs before code
generation. It matches interleaved memory operations to target-specific
intrinsics (that are later lowered to load and store multiple instructions on
ARM/AArch64). We place tests for similar passes (e.g., GlobalMergePass) under
test/Transforms. This patch moves the InterleavedAccessPass tests out of
test/CodeGen and into target-specific directories under
test/Transforms/InterleavedAccess.

Although the pass is an IR pass, many of the existing tests were llc tests
rather opt tests. For example, the tests would check for ldN/stN instructions
generated by llc rather than the intrinsic calls the pass actually inserts.
Thus, this patch updates all tests to be opt tests that check for the inserted
intrinsics. We already have separate CodeGen tests that ensure we lower the
interleaved access intrinsics to their corresponding ldN/stN instructions. In
addition to migrating the tests to opt, this patch also performs some minor
clean-up (to ensure consistent naming, etc.).

Differential Revision: https://reviews.llvm.org/D29184

llvm-svn: 293309

1 files changed, 0 insertions, 86 deletions

diff --git a/llvm/test/CodeGen/ARM/arm-interleaved-accesses-extract-user.ll b/llvm/test/CodeGen/ARM/arm-interleaved-accesses-extract-user.ll
deleted file mode 100644
index 620cb635641..00000000000
--- a/llvm/test/CodeGen/ARM/arm-interleaved-accesses-extract-user.ll
+++ /dev/null
@@ -1,86 +0,0 @@
-; RUN: opt < %s -mtriple=arm-eabi -mattr=+neon -interleaved-access -S | FileCheck %s
-
-; CHECK-LABEL: @extract_user_basic(
-; CHECK: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
-; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %vldN, 0
-; CHECK: extractelement <4 x i32> %[[R]], i64 1
-define void @extract_user_basic(<8 x i32>* %A, i1 %C) {
-entry:
-  %L = load <8 x i32>, <8 x i32>* %A, align 8
-  %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-  br i1 %C, label %if.then, label %if.merge
-
-if.then:
-  %E = extractelement <8 x i32> %L, i32 2
-  br label %if.merge
-
-if.merge:
-  ret void
-}
-
-; CHECK-LABEL: @extract_user_multi(
-; CHECK: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
-; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %vldN, 0
-; CHECK: extractelement <4 x i32> %[[R]], i64 0
-; CHECK: extractelement <4 x i32> %[[R]], i64 1
-define void @extract_user_multi(<8 x i32>* %A, i1 %C) {
-entry:
-  %L = load <8 x i32>, <8 x i32>* %A, align 8
-  %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-  br i1 %C, label %if.then, label %if.merge
-
-if.then:
-  %E1 = extractelement <8 x i32> %L, i32 0
-  br label %if.merge
-
-if.merge:
-  %E2 = extractelement <8 x i32> %L, i32 2
-  ret void
-}
-
-; CHECK-LABEL: @extract_user_multi_no_dom(
-; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
-define void @extract_user_multi_no_dom(<8 x i32>* %A, i1 %C) {
-entry:
-  %L = load <8 x i32>, <8 x i32>* %A, align 8
-  %E1 = extractelement <8 x i32> %L, i32 0
-  br i1 %C, label %if.then, label %if.merge
-
-if.then:
-  %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-  %E2 = extractelement <8 x i32> %L, i32 2
-  br label %if.merge
-
-if.merge:
-  ret void
-}
-
-; CHECK-LABEL: @extract_user_wrong_const_index(
-; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
-define void @extract_user_wrong_const_index(<8 x i32>* %A) {
-entry:
-  %L = load <8 x i32>, <8 x i32>* %A, align 8
-  %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-  %E = extractelement <8 x i32> %L, i32 1
-  ret void
-}
-
-; CHECK-LABEL: @extract_user_undef_index(
-; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
-define void @extract_user_undef_index(<8 x i32>* %A) {
-entry:
-  %L = load <8 x i32>, <8 x i32>* %A, align 8
-  %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-  %E = extractelement <8 x i32> %L, i32 undef
-  ret void
-}
-
-; CHECK-LABEL: @extract_user_var_index(
-; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
-define void @extract_user_var_index(<8 x i32>* %A, i32 %I) {
-entry:
-  %L = load <8 x i32>, <8 x i32>* %A, align 8
-  %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-  %E = extractelement <8 x i32> %L, i32 %I
-  ret void
-}