[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).

The benchmarking summarized in
http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed
this is beneficial for a wide range of cores.

As is to be expected, quite a few small adaptations are needed to the
regressions tests, as the difference in scheduling results in:
- Quite a few small instruction schedule differences.
- A few changes in register allocation decisions caused by different
 instruction schedules.
- A few changes in IfConversion decisions, due to a difference in
 instruction schedule and/or the estimated cost of a branch mispredict.

llvm-svn: 306514

1 files changed, 2 insertions, 2 deletions

diff --git a/llvm/test/CodeGen/ARM/arg-copy-elide.ll b/llvm/test/CodeGen/ARM/arg-copy-elide.ll
index 739b560b083..625b5707340 100644
--- a/llvm/test/CodeGen/ARM/arg-copy-elide.ll
+++ b/llvm/test/CodeGen/ARM/arg-copy-elide.ll
@@ -31,8 +31,8 @@ entry:
 
 ; CHECK-LABEL: use_arg:
 ; CHECK: push {[[csr:[^ ]*]], lr}
-; CHECK: ldr [[csr]], [sp, #8]
 ; CHECK: add r0, sp, #8
+; CHECK: ldr [[csr]], [sp, #8]
 ; CHECK: bl addrof_i32
 ; CHECK: mov r0, [[csr]]
 ; CHECK: pop {[[csr]], pc}
@@ -50,8 +50,8 @@ entry:
 ; CHECK: push    {r4, r5, r11, lr}
 ; CHECK: sub     sp, sp, #8
 ; CHECK: ldr     r4, [sp, #28]
-; CHECK: ldr     r5, [sp, #24]
 ; CHECK: mov     r0, sp
+; CHECK: ldr     r5, [sp, #24]
 ; CHECK: str     r4, [sp, #4]
 ; CHECK: str     r5, [sp]
 ; CHECK: bl      addrof_i64