[ARM] Adjust AND immediates to make them cheaper to select.

LLVM normally prefers to minimize the number of bits set in an AND
immediate, but that doesn't always match the available ARM instructions.
In Thumb1 mode, prefer uxtb or uxth where possible; otherwise, prefer
a two-instruction sequence movs+ands or movs+bics.

Some potential improvements outlined in
ARMTargetLowering::targetShrinkDemandedConstant, but seems to work
pretty well already.

The ARMISelDAGToDAG fix ensures we don't generate an invalid UBFX
instruction due to a larger-than-expected mask. (It's orthogonal, in
some sense, but as far as I can tell it's either impossible or nearly
impossible to reproduce the bug without this change.)

According to my testing, this seems to consistently improve codesize by
a small amount by forming bic more often for ISD::AND with an immediate.

Differential Revision: https://reviews.llvm.org/D50030

llvm-svn: 339472

1 files changed, 4 insertions, 5 deletions

diff --git a/llvm/test/CodeGen/ARM/and-cmpz.ll b/llvm/test/CodeGen/ARM/and-cmpz.ll
index fb5f8fe280f..b327f04ba06 100644
--- a/llvm/test/CodeGen/ARM/and-cmpz.ll
+++ b/llvm/test/CodeGen/ARM/and-cmpz.ll
@@ -89,11 +89,10 @@ false:
 }
 
 ; CHECK-LABEL: i16_cmpz:
-; T1:      movs    r2, #127
-; T1-NEXT: lsls    r2, r2, #9
-; T1-NEXT: ands    r2, r0
-; T1-NEXT: lsrs    r0, r2, #9
-; T2:      and     r0, r0, #65024
+; T1:      uxth    r0, r0
+; T1-NEXT: lsrs    r0, r0, #9
+; T1-NEXT: bne
+; T2:      uxth    r0, r0
 ; T2-NEXT: movs    r2, #0
 ; T2-NEXT: cmp.w   r2, r0, lsr #9
 define void @i16_cmpz(i16 %x, void (i32)* %foo) {