diff options
author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
---|---|---|
committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll | |
parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll')
-rw-r--r-- | llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll b/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll index 5ad87191efe..600fb6aa44b 100644 --- a/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll +++ b/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll @@ -31,9 +31,9 @@ entry: ; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]! ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128] %retval = alloca <16 x float>, align 16 - %0 = load <16 x float>* @T3_retval, align 16 + %0 = load <16 x float>, <16 x float>* @T3_retval, align 16 store <16 x float> %0, <16 x float>* %retval - %1 = load <16 x float>* %retval + %1 = load <16 x float>, <16 x float>* %retval store <16 x float> %1, <16 x float>* %agg.result, align 16 ret void } @@ -66,9 +66,9 @@ entry: ; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]! ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128] %retval = alloca <16 x float>, align 16 - %0 = load <16 x float>* @T3_retval, align 16 + %0 = load <16 x float>, <16 x float>* @T3_retval, align 16 store <16 x float> %0, <16 x float>* %retval - %1 = load <16 x float>* %retval + %1 = load <16 x float>, <16 x float>* %retval store <16 x float> %1, <16 x float>* %agg.result, align 16 ret void } |