ARM: address WOA unsigned division overflow crash

Building on r253865 the crash is not limited to signed overflows.

Disable custom handling of unsigned 32-bit and 64-bit integer divide.
Add test cases for both 32-bit and 64-bit unsigned integer overflow.

llvm-svn: 254158

3 files changed, 63 insertions, 31 deletions

diff --git a/llvm/test/CodeGen/ARM/Windows/division.ll b/llvm/test/CodeGen/ARM/Windows/division.ll
index 9ff3b7c781c..b3ef9c6d278 100644
--- a/llvm/test/CodeGen/ARM/Windows/division.ll
+++ b/llvm/test/CodeGen/ARM/Windows/division.ll
@@ -1,6 +1,15 @@
 ; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s
 
+define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) {
+entry:
+  %div = sdiv i32 %divident, %divisor
+  ret i32 %div
+}
+
+; CHECK-LABEL: sdiv32
+; CHECK: b __rt_sdiv
+
 define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
 entry:
   %div = udiv i32 %divident, %divisor
@@ -8,9 +17,16 @@ entry:
 }
 
 ; CHECK-LABEL: udiv32:
-; CHECK: cbz r0
-; CHECK: bl __rt_udiv
-; CHECK: udf.w #249
+; CHECK: b __rt_udiv
+
+define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
+entry:
+  %div = sdiv i64 %divident, %divisor
+  ret i64 %div
+}
+
+; CHECK-LABEL: sdiv64
+; CHECK: bl __rt_sdiv64
 
 define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
 entry:
@@ -19,8 +35,4 @@ entry:
 }
 
 ; CHECK-LABEL: udiv64:
-; CHECK: orr.w r12, r0, r1
-; CHECK-NEXT: cbz r12
 ; CHECK: bl __rt_udiv64
-; CHECK: udf.w #249
-
diff --git a/llvm/test/CodeGen/ARM/Windows/libcalls.ll b/llvm/test/CodeGen/ARM/Windows/libcalls.ll
index fcc4ef016c2..d8b498a40d9 100644
--- a/llvm/test/CodeGen/ARM/Windows/libcalls.ll
+++ b/llvm/test/CodeGen/ARM/Windows/libcalls.ll
@@ -1,24 +1,6 @@
 ; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s
 
-define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) {
-entry:
-  %div = sdiv i32 %divident, %divisor
-  ret i32 %div
-}
-
-; CHECK-LABEL: sdiv32
-; CHECK: b __rt_sdiv
-
-define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
-entry:
-  %div = sdiv i64 %divident, %divisor
-  ret i64 %div
-}
-
-; CHECK-LABEL: sdiv64
-; CHECK: bl __rt_sdiv64
-
 define arm_aapcs_vfpcc i64 @stoi64(float %f) {
 entry:
   %conv = fptosi float %f to i64
diff --git a/llvm/test/CodeGen/ARM/Windows/overflow.ll b/llvm/test/CodeGen/ARM/Windows/overflow.ll
index 23f5ee52224..5f74f25ac22 100644
--- a/llvm/test/CodeGen/ARM/Windows/overflow.ll
+++ b/llvm/test/CodeGen/ARM/Windows/overflow.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple thumbv7-windows-gnu -filetype asm -o - %s
 
-define i32 @divoverflow32(i32 %a, i32 %b) {
+define i32 @divsoverflow32(i32 %a, i32 %b) {
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = load i32, i32* %1, align 4
@@ -9,7 +9,7 @@ define i32 @divoverflow32(i32 %a, i32 %b) {
   %6 = sdiv i32 -2147483647, %3
   %7 = icmp sgt i32 %5, %6
   br i1 %7, label %8, label %9
-  call void (...) @abort_impl32()
+  call void (...) @abort_simpl32()
   unreachable
   %10 = load i32, i32* %1, align 4
   %11 = load i32, i32* %2, align 4
@@ -17,9 +17,9 @@ define i32 @divoverflow32(i32 %a, i32 %b) {
   ret i32 %12
 }
 
-declare void @abort_impl32(...)
+declare void @abort_simpl32(...)
 
-define i64 @divoverflow64(i64 %a, i64 %b) {
+define i64 @divsoverflow64(i64 %a, i64 %b) {
   %1 = alloca i64, align 8
   %2 = alloca i64, align 8
   %3 = load i64, i64* %1, align 8
@@ -28,7 +28,7 @@ define i64 @divoverflow64(i64 %a, i64 %b) {
   %6 = sdiv i64 -9223372036854775808, %3
   %7 = icmp sgt i64 %5, %6
   br i1 %7, label %8, label %9
-  call void (...) @abort_impl64()
+  call void (...) @abort_simpl64()
   unreachable
   %10 = load i64, i64* %1, align 8
   %11 = load i64, i64* %2, align 8
@@ -36,4 +36,42 @@ define i64 @divoverflow64(i64 %a, i64 %b) {
   ret i64 %12
 }
 
-declare void @abort_impl64(...)
+declare void @abort_simpl64(...)
+
+define i32 @divuoverflow32(i32 %a, i32 %b) {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = load i32, i32* %1, align 4
+  %4 = load i32, i32* %2, align 4
+  %5 = sub nsw i32 0, %4
+  %6 = udiv i32 4294967296, %3
+  %7 = icmp sgt i32 %5, %6
+  br i1 %7, label %8, label %9
+  call void (...) @abort_uimpl32()
+  unreachable
+  %10 = load i32, i32* %1, align 4
+  %11 = load i32, i32* %2, align 4
+  %12 = mul nsw i32 %10, %11
+  ret i32 %12
+}
+
+declare void @abort_uimpl32(...)
+
+define i64 @divuoverflow64(i64 %a, i64 %b) {
+  %1 = alloca i64, align 8
+  %2 = alloca i64, align 8
+  %3 = load i64, i64* %1, align 8
+  %4 = load i64, i64* %2, align 8
+  %5 = sub nsw i64 0, %4
+  %6 = udiv i64 18446744073709551616, %3
+  %7 = icmp sgt i64 %5, %6
+  br i1 %7, label %8, label %9
+  call void (...) @abort_uimpl64()
+  unreachable
+  %10 = load i64, i64* %1, align 8
+  %11 = load i64, i64* %2, align 8
+  %12 = mul nsw i64 %10, %11
+  ret i64 %12
+}
+
+declare void @abort_uimpl64(...)