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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-03 00:30:47 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-03 00:30:47 +0000 |
| commit | 4f3472deb28b772c82323a849eddd9b67f1cdc31 (patch) | |
| tree | 9cc550a990022c170d44535e9fa379ba4f344bc0 /llvm/test/CodeGen/ARM/Windows | |
| parent | c04aab9c0646461bc187808920b3d5ee7f5cc5ab (diff) | |
| download | bcm5719-llvm-4f3472deb28b772c82323a849eddd9b67f1cdc31.tar.gz bcm5719-llvm-4f3472deb28b772c82323a849eddd9b67f1cdc31.zip | |
CodeGen: Set hasSideEffects = 0 on BUNDLE
The BUNDLE itself should not have side effects, and this is a property
of instructions inside the bundle. The hasProperty check already
searches for any member instructions, which was pointless since it was
overridden by this bit.
Allows me to distinguish bundles that have side effects vs. do not in
a future patch. Also fixes an unnecessary scheduling barrier in the
bundle AMDGPU uses to get PC relative addresses.
llvm-svn: 364984
Diffstat (limited to 'llvm/test/CodeGen/ARM/Windows')
| -rw-r--r-- | llvm/test/CodeGen/ARM/Windows/tls.ll | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/ARM/Windows/tls.ll b/llvm/test/CodeGen/ARM/Windows/tls.ll index 2c38ad3e58f..931621a5d39 100644 --- a/llvm/test/CodeGen/ARM/Windows/tls.ll +++ b/llvm/test/CodeGen/ARM/Windows/tls.ll @@ -15,11 +15,10 @@ define i32 @f() { ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 -; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] - +; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] @@ -36,11 +35,10 @@ define i32 @e() { ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 -; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] - +; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] @@ -57,11 +55,10 @@ define i32 @d() { ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 -; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] - +; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] @@ -78,11 +75,10 @@ define i32 @c() { ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 -; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] - +; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] @@ -99,11 +95,10 @@ define i32 @b() { ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 -; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] - +; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] @@ -120,11 +115,10 @@ define i16 @a() { ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 -; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] - +; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] @@ -141,11 +135,10 @@ define i8 @Z() { ; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 -; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index ; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index ; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] - +; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] ; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] ; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]] |
