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| author | Sam Parker <sam.parker@arm.com> | 2019-09-04 08:41:34 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2019-09-04 08:41:34 +0000 |
| commit | fea532230bf4cf677d0ae6028eedf0135aa8b9e2 (patch) | |
| tree | ad62034c85649bc6991de85498e3e47b7adbbd67 /llvm/test/CodeGen/ARM/ParallelDSP/overlapping.ll | |
| parent | 16d12847c1b43cbea908f6defef0be434e71d7f6 (diff) | |
| download | bcm5719-llvm-fea532230bf4cf677d0ae6028eedf0135aa8b9e2.tar.gz bcm5719-llvm-fea532230bf4cf677d0ae6028eedf0135aa8b9e2.zip | |
[ARM][ParallelDSP] SExt mul for accumulation
For any unpaired muls, we accumulate them as an input to the
reduction. Check the type of the mul and perform a sext if the
existing accumlator input type is not the same.
Differential Revision: https://reviews.llvm.org/D66993
llvm-svn: 370851
Diffstat (limited to 'llvm/test/CodeGen/ARM/ParallelDSP/overlapping.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/ParallelDSP/overlapping.ll | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/overlapping.ll b/llvm/test/CodeGen/ARM/ParallelDSP/overlapping.ll index a071ec3e748..1f4b141b7a0 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/overlapping.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/overlapping.ll @@ -42,6 +42,52 @@ entry: ret i32 %res } +; TODO: Is it really best to generate smlald for the first instruction? Does +; this just increase register pressure unnecessarily? +; CHECK-LABEL: overlap_64_1 +; CHECK: [[ADDR_A_1:%[^ ]+]] = getelementptr i16, i16* %a, i32 1 +; CHECK: [[ADDR_B_1:%[^ ]+]] = getelementptr i16, i16* %b, i32 1 +; CHECK: [[CAST_A:%[^ ]+]] = bitcast i16* %a to i32* +; CHECK: [[LD_A:%[^ ]+]] = load i32, i32* [[CAST_A]] +; CHECK: [[CAST_B:%[^ ]+]] = bitcast i16* %b to i32* +; CHECK: [[LD_B:%[^ ]+]] = load i32, i32* [[CAST_B]] +; CHECK: [[CAST_A_1:%[^ ]+]] = bitcast i16* [[ADDR_A_1]] to i32* +; CHECK: [[LD_A_1:%[^ ]+]] = load i32, i32* [[CAST_A_1]] +; CHECK: [[CAST_B_1:%[^ ]+]] = bitcast i16* [[ADDR_B_1]] to i32* +; CHECK: [[LD_B_1:%[^ ]+]] = load i32, i32* [[CAST_B_1]] +; CHECK: [[ACC:%[^ ]+]] = call i64 @llvm.arm.smlald(i32 [[LD_A_1]], i32 [[LD_B_1]], i64 %acc) +; CHECK: [[RES:%[^ ]+]] = call i64 @llvm.arm.smlald(i32 [[LD_A]], i32 [[LD_B]], i64 [[ACC]]) +; CHECK: ret i64 [[RES]] +define i64 @overlap_64_1(i16* %a, i16* %b, i64 %acc) { +entry: + %addr.a.1 = getelementptr i16, i16* %a, i32 1 + %addr.b.1 = getelementptr i16, i16* %b, i32 1 + %ld.a.0 = load i16, i16* %a + %sext.a.0 = sext i16 %ld.a.0 to i32 + %ld.b.0 = load i16, i16* %b + %ld.a.1 = load i16, i16* %addr.a.1 + %ld.b.1 = load i16, i16* %addr.b.1 + %sext.a.1 = sext i16 %ld.a.1 to i32 + %sext.b.1 = sext i16 %ld.b.1 to i32 + %sext.b.0 = sext i16 %ld.b.0 to i32 + %mul.0 = mul i32 %sext.a.0, %sext.b.0 + %mul.1 = mul i32 %sext.a.1, %sext.b.1 + %addr.a.2 = getelementptr i16, i16* %a, i32 2 + %addr.b.2 = getelementptr i16, i16* %b, i32 2 + %ld.a.2 = load i16, i16* %addr.a.2 + %ld.b.2 = load i16, i16* %addr.b.2 + %sext.a.2 = sext i16 %ld.a.2 to i32 + %sext.b.2 = sext i16 %ld.b.2 to i32 + %mul.2 = mul i32 %sext.a.2, %sext.b.2 + %add = add i32 %mul.0, %mul.1 + %add.1 = add i32 %mul.1, %mul.2 + %sext.add = sext i32 %add to i64 + %sext.add.1 = sext i32 %add.1 to i64 + %add.2 = add i64 %sext.add.1, %sext.add + %res = add i64 %add.2, %acc + ret i64 %res +} + ; CHECK-LABEL: overlap_2 ; CHECK: [[ADDR_A_1:%[^ ]+]] = getelementptr i16, i16* %a, i32 1 ; CHECK: [[ADDR_B_1:%[^ ]+]] = getelementptr i16, i16* %b, i32 1 |
