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| author | Hiroshi Yamauchi <yamauchi@google.com> | 2019-12-05 09:39:37 -0800 |
|---|---|---|
| committer | Hiroshi Yamauchi <yamauchi@google.com> | 2019-12-09 12:42:59 -0800 |
| commit | d9ae493937c7fff67cb0afba133c6f9872db784a (patch) | |
| tree | e2ed33de6c22380c0bf59e515300322c4fa30a1f /llvm/test/CodeGen/ARM/O3-pipeline.ll | |
| parent | 505aa2410db6d089279da1a271903ce2633764f6 (diff) | |
| download | bcm5719-llvm-d9ae493937c7fff67cb0afba133c6f9872db784a.tar.gz bcm5719-llvm-d9ae493937c7fff67cb0afba133c6f9872db784a.zip | |
[PGO][PGSO] Instrument the code gen / target passes.
Summary:
Split off of D67120.
Add the profile guided size optimization instrumentation / queries in the code
gen or target passes. This doesn't enable the size optimizations in those passes
yet as they are currently disabled in shouldOptimizeForSize (for non-IR pass
queries).
A second try after reverted D71072.
Reviewers: davidxl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71149
Diffstat (limited to 'llvm/test/CodeGen/ARM/O3-pipeline.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/O3-pipeline.ll | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll index 3fd35bd1e9d..4188ce759eb 100644 --- a/llvm/test/CodeGen/ARM/O3-pipeline.ll +++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll @@ -19,6 +19,9 @@ ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Merge contiguous icmps into a memcmp +; CHECK-NEXT: Natural Loop Information +; CHECK-NEXT: Lazy Branch Probability Analysis +; CHECK-NEXT: Lazy Block Frequency Analysis ; CHECK-NEXT: Expand memcmp() to load/stores ; CHECK-NEXT: Lower Garbage Collection Instructions ; CHECK-NEXT: Shadow Stack GC Lowering @@ -67,8 +70,11 @@ ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Branch Probability Analysis +; CHECK-NEXT: Lazy Branch Probability Analysis +; CHECK-NEXT: Lazy Block Frequency Analysis ; CHECK-NEXT: ARM Instruction Selection ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions +; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Early Tail Duplication ; CHECK-NEXT: Optimize machine instruction PHIs ; CHECK-NEXT: Slot index numbering @@ -124,6 +130,7 @@ ; CHECK-NEXT: Shrink Wrapping analysis ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; CHECK-NEXT: Control Flow Optimizer +; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Tail Duplication ; CHECK-NEXT: Machine Copy Propagation Pass ; CHECK-NEXT: Post-RA pseudo instruction expansion pass |
