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| author | Craig Topper <craig.topper@intel.com> | 2018-01-23 05:45:52 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-23 05:45:52 +0000 |
| commit | c92edd994ea678111d6c28eed1c1a453a5aa292c (patch) | |
| tree | 891567f7150f34b9c354e03a349ae8e4069fb6b6 /llvm/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll | |
| parent | e5aea259809d5bd828acdcaa54de2eff5dcc74dc (diff) | |
| download | bcm5719-llvm-c92edd994ea678111d6c28eed1c1a453a5aa292c.tar.gz bcm5719-llvm-c92edd994ea678111d6c28eed1c1a453a5aa292c.zip | |
[X86] Don't reorder (srl (and X, C1), C2) if (and X, C1) can be matched as a movzx
Summary:
If we can match as a zero extend there's no need to flip the order to get an encoding benefit. As movzx is 3 bytes with independent source/dest registers. The shortest 'and' we could make is also 3 bytes unless we get lucky in the register allocator and its on AL/AX/EAX which have a 2 byte encoding.
This patch was more impressive before r322957 went in. It removed some of the same Ands that got deleted by that patch.
Reviewers: spatel, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42313
llvm-svn: 323175
Diffstat (limited to 'llvm/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll')
0 files changed, 0 insertions, 0 deletions
