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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-16 20:35:23 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-16 20:35:23 +0000 |
| commit | 3b36bb1d8780caeb122ee86cf2f44e397cb028ea (patch) | |
| tree | 8bfac477c9af17ec001ff7b7f479d6cd7dd5e91f /llvm/test/CodeGen/AMDGPU/xor.ll | |
| parent | 1b9560ffd61f3f4c2089c4971ebce0cfb4932adf (diff) | |
| download | bcm5719-llvm-3b36bb1d8780caeb122ee86cf2f44e397cb028ea.tar.gz bcm5719-llvm-3b36bb1d8780caeb122ee86cf2f44e397cb028ea.zip | |
AMDGPU: Enable ConstrainCopy DAG mutation
This fixes a probably unintended divergence from the default
scheduler behavior.
llvm-svn: 287146
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/xor.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/xor.ll | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/xor.ll b/llvm/test/CodeGen/AMDGPU/xor.ll index 53f4c0a9174..bc8016c268f 100644 --- a/llvm/test/CodeGen/AMDGPU/xor.ll +++ b/llvm/test/CodeGen/AMDGPU/xor.ll @@ -206,10 +206,11 @@ define void @scalar_xor_literal_multi_use_i64(i64 addrspace(1)* %out, i64 %a, i6 ; SI-NOT: xor_b32 ; SI: s_xor_b32 s[[VAL_LO]], s[[VAL_LO]], 63 ; SI-NOT: xor_b32 -; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[VAL_LO]] -; SI-NOT: xor_b32 ; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[VAL_HI]] ; SI-NOT: xor_b32 +; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[VAL_LO]] + +; SI-NOT: xor_b32 ; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} define void @scalar_xor_inline_imm_i64(i64 addrspace(1)* %out, i64 %a) { %or = xor i64 %a, 63 |
