diff options
| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-08-16 04:43:49 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-08-16 04:43:49 +0000 |
| commit | a9487d92d74c60d9d65a2880d08901354f4eea7a (patch) | |
| tree | 20d9a8df89add53701e1939f92c571661b1b326d /llvm/test/CodeGen/AMDGPU/write_register.ll | |
| parent | 0c6374e51325d3f4f69f091b2ac85ff273274afe (diff) | |
| download | bcm5719-llvm-a9487d92d74c60d9d65a2880d08901354f4eea7a.tar.gz bcm5719-llvm-a9487d92d74c60d9d65a2880d08901354f4eea7a.zip | |
[AMDGPU] Eliminate no effect instructions before s_endpgm
Differential Revision: https://reviews.llvm.org/D36585
llvm-svn: 310987
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/write_register.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/write_register.ll | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/write_register.ll b/llvm/test/CodeGen/AMDGPU/write_register.ll index 9c62e003dde..0ca92f90c22 100644 --- a/llvm/test/CodeGen/AMDGPU/write_register.ll +++ b/llvm/test/CodeGen/AMDGPU/write_register.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s declare void @llvm.write_register.i32(metadata, i32) #0 declare void @llvm.write_register.i64(metadata, i64) #0 @@ -8,6 +8,7 @@ define amdgpu_kernel void @test_write_m0(i32 %val) #0 { call void @llvm.write_register.i32(metadata !0, i32 0) call void @llvm.write_register.i32(metadata !0, i32 -1) call void @llvm.write_register.i32(metadata !0, i32 %val) + call void @llvm.amdgcn.wave.barrier() #1 ret void } @@ -19,6 +20,7 @@ define amdgpu_kernel void @test_write_exec(i64 %val) #0 { call void @llvm.write_register.i64(metadata !1, i64 0) call void @llvm.write_register.i64(metadata !1, i64 -1) call void @llvm.write_register.i64(metadata !1, i64 %val) + call void @llvm.amdgcn.wave.barrier() #1 ret void } @@ -30,6 +32,7 @@ define amdgpu_kernel void @test_write_flat_scratch(i64 %val) #0 { call void @llvm.write_register.i64(metadata !2, i64 0) call void @llvm.write_register.i64(metadata !2, i64 -1) call void @llvm.write_register.i64(metadata !2, i64 %val) + call void @llvm.amdgcn.wave.barrier() #1 ret void } @@ -39,6 +42,7 @@ define amdgpu_kernel void @test_write_flat_scratch(i64 %val) #0 { define amdgpu_kernel void @test_write_flat_scratch_lo(i32 %val) #0 { call void @llvm.write_register.i32(metadata !3, i32 0) call void @llvm.write_register.i32(metadata !3, i32 %val) + call void @llvm.amdgcn.wave.barrier() #1 ret void } @@ -48,6 +52,7 @@ define amdgpu_kernel void @test_write_flat_scratch_lo(i32 %val) #0 { define amdgpu_kernel void @test_write_flat_scratch_hi(i32 %val) #0 { call void @llvm.write_register.i32(metadata !4, i32 0) call void @llvm.write_register.i32(metadata !4, i32 %val) + call void @llvm.amdgcn.wave.barrier() #1 ret void } @@ -57,6 +62,7 @@ define amdgpu_kernel void @test_write_flat_scratch_hi(i32 %val) #0 { define amdgpu_kernel void @test_write_exec_lo(i32 %val) #0 { call void @llvm.write_register.i32(metadata !5, i32 0) call void @llvm.write_register.i32(metadata !5, i32 %val) + call void @llvm.amdgcn.wave.barrier() #1 ret void } @@ -66,10 +72,14 @@ define amdgpu_kernel void @test_write_exec_lo(i32 %val) #0 { define amdgpu_kernel void @test_write_exec_hi(i32 %val) #0 { call void @llvm.write_register.i32(metadata !6, i32 0) call void @llvm.write_register.i32(metadata !6, i32 %val) + call void @llvm.amdgcn.wave.barrier() #1 ret void } +declare void @llvm.amdgcn.wave.barrier() #1 + attributes #0 = { nounwind } +attributes #1 = { convergent nounwind } !0 = !{!"m0"} !1 = !{!"exec"} |
