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| author | Matthias Braun <matze@braunis.de> | 2015-12-03 03:01:10 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2015-12-03 03:01:10 +0000 |
| commit | 2fd672a221eb0b537615bfb9d42ce6a824f33dbc (patch) | |
| tree | ed1ec739dea2cde10c16a87d6ab32bd7dbb76738 /llvm/test/CodeGen/AMDGPU/work-item-intrinsics.ll | |
| parent | 311fef6ea523374d8ffc723fb124af178e435749 (diff) | |
| download | bcm5719-llvm-2fd672a221eb0b537615bfb9d42ce6a824f33dbc.tar.gz bcm5719-llvm-2fd672a221eb0b537615bfb9d42ce6a824f33dbc.zip | |
Revert "ScheduleDAGInstrs: Rework schedule graph builder."
This works mostly fine but breaks some stage 1 builders when compiling
compiler-rt on i386. Revert for further investigation as I can't see an
obvious cause/fix.
This reverts commit r254577.
llvm-svn: 254586
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/work-item-intrinsics.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/work-item-intrinsics.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/work-item-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/work-item-intrinsics.ll index f420ec9c7d2..a704a23b0f9 100644 --- a/llvm/test/CodeGen/AMDGPU/work-item-intrinsics.ll +++ b/llvm/test/CodeGen/AMDGPU/work-item-intrinsics.ll @@ -7,7 +7,7 @@ ; FUNC-LABEL: {{^}}ngroups_x: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[0].X +; EG: MOV [[VAL]], KC0[0].X ; HSA: .amd_kernel_code_t @@ -38,7 +38,7 @@ entry: ; FUNC-LABEL: {{^}}ngroups_y: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y +; EG: MOV [[VAL]], KC0[0].Y ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4 @@ -53,7 +53,7 @@ entry: ; FUNC-LABEL: {{^}}ngroups_z: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z +; EG: MOV [[VAL]], KC0[0].Z ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8 @@ -68,7 +68,7 @@ entry: ; FUNC-LABEL: {{^}}global_size_x: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[0].W +; EG: MOV [[VAL]], KC0[0].W ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc @@ -83,7 +83,7 @@ entry: ; FUNC-LABEL: {{^}}global_size_y: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[1].X +; EG: MOV [[VAL]], KC0[1].X ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10 @@ -98,7 +98,7 @@ entry: ; FUNC-LABEL: {{^}}global_size_z: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y +; EG: MOV [[VAL]], KC0[1].Y ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14 |
