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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-05-21 03:55:07 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-05-21 03:55:07 +0000 |
| commit | 7f9eabd2c245ce2d191f7e456aef068c21638a00 (patch) | |
| tree | 05c2cf59aaa1cf5e3d1bdc6e7dc59b077991647a /llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll | |
| parent | 97565ded80aea4422cbc3b8d2a4ad636a88071e2 (diff) | |
| download | bcm5719-llvm-7f9eabd2c245ce2d191f7e456aef068c21638a00.tar.gz bcm5719-llvm-7f9eabd2c245ce2d191f7e456aef068c21638a00.zip | |
AMDGPU: Define priorities for register classes
Allocating larger register classes first should give better allocation
results (and more importantly for myself, make the lit tests more stable
with respect to scheduler changes).
Patch by Matthias Braun
llvm-svn: 270312
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll b/llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll index d2703453d40..38dbf2794fc 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-flat.ll @@ -6,9 +6,9 @@ ; for the original bug. ; GCN: {{^}}test: -; GCN: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[DATA:v[0-9]+]] -; GCN: s_waitcnt vmcnt(0) lgkmcnt(0) -; GCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}] +; XGCN: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[DATA:v[0-9]+]] +; XGCN: s_waitcnt vmcnt(0) lgkmcnt(0) +; XGCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}] define void @test(i32 addrspace(1)* %out, i32 %in) { store volatile i32 0, i32 addrspace(1)* %out %val = load volatile i32, i32 addrspace(1)* %out |
