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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-03-21 21:39:51 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-03-21 21:39:51 +0000 |
| commit | 3dbeefa978fb7e7b231b249f9cd90c67b9e83277 (patch) | |
| tree | d74bf7fe30e44588d573919f3625edacb2586112 /llvm/test/CodeGen/AMDGPU/vector-alloca.ll | |
| parent | f6021ecddc73d14c94ad70938250d58f330795be (diff) | |
| download | bcm5719-llvm-3dbeefa978fb7e7b231b249f9cd90c67b9e83277.tar.gz bcm5719-llvm-3dbeefa978fb7e7b231b249f9cd90c67b9e83277.zip | |
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
Currently the default C calling convention functions are treated
the same as compute kernels. Make this explicit so the default
calling convention can be changed to a non-kernel.
Converted with perl -pi -e 's/define void/define amdgpu_kernel void/'
on the relevant test directories (and undoing in one place that actually
wanted a non-kernel).
llvm-svn: 298444
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/vector-alloca.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/vector-alloca.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/vector-alloca.ll b/llvm/test/CodeGen/AMDGPU/vector-alloca.ll index 7dcf36f144a..03cf725601b 100644 --- a/llvm/test/CodeGen/AMDGPU/vector-alloca.ll +++ b/llvm/test/CodeGen/AMDGPU/vector-alloca.ll @@ -15,7 +15,7 @@ ; EG: MOV ; EG: MOV ; EG: MOVA_INT -define void @vector_read(i32 addrspace(1)* %out, i32 %index) { +define amdgpu_kernel void @vector_read(i32 addrspace(1)* %out, i32 %index) { entry: %tmp = alloca [4 x i32] %x = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0 @@ -44,7 +44,7 @@ entry: ; EG: MOV ; EG: MOVA_INT ; EG: MOVA_INT -define void @vector_write(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) { +define amdgpu_kernel void @vector_write(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) { entry: %tmp = alloca [4 x i32] %x = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0 @@ -71,7 +71,7 @@ entry: ; FUNC-LABEL: {{^}}bitcast_gep: ; EG: STORE_RAW -define void @bitcast_gep(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) { +define amdgpu_kernel void @bitcast_gep(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) { entry: %tmp = alloca [4 x i32] %x = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0 @@ -93,7 +93,7 @@ entry: ; OPT-LABEL: @vector_read_bitcast_gep( ; OPT: %0 = extractelement <4 x i32> <i32 1065353216, i32 1, i32 2, i32 3>, i32 %index ; OPT: store i32 %0, i32 addrspace(1)* %out, align 4 -define void @vector_read_bitcast_gep(i32 addrspace(1)* %out, i32 %index) { +define amdgpu_kernel void @vector_read_bitcast_gep(i32 addrspace(1)* %out, i32 %index) { entry: %tmp = alloca [4 x i32] %x = getelementptr inbounds [4 x i32], [4 x i32]* %tmp, i32 0, i32 0 @@ -121,7 +121,7 @@ entry: ; OPT: store float ; OPT: store float ; OPT: load float -define void @vector_read_bitcast_alloca(float addrspace(1)* %out, i32 %index) { +define amdgpu_kernel void @vector_read_bitcast_alloca(float addrspace(1)* %out, i32 %index) { entry: %tmp = alloca [4 x i32] %tmp.bc = bitcast [4 x i32]* %tmp to [4 x float]* |
