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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-01-09 21:34:43 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2018-01-09 21:34:43 +0000 |
| commit | 6eaad1e5397dc84c7dbb78be4fa433bcd6fb137f (patch) | |
| tree | 913b778f0fc2c78591c1a0fe7460de17ba98ff1b /llvm/test/CodeGen/AMDGPU/uniform-cfg.ll | |
| parent | f0ef137bd0c34f984090638df8c62ad55d790694 (diff) | |
| download | bcm5719-llvm-6eaad1e5397dc84c7dbb78be4fa433bcd6fb137f.tar.gz bcm5719-llvm-6eaad1e5397dc84c7dbb78be4fa433bcd6fb137f.zip | |
[AMDGPU] Fixed incorrect uniform branch condition
Summary:
I had a case where multiple nested uniform ifs resulted in code that did
v_cmp comparisons, combining the results with s_and_b64, s_or_b64 and
s_xor_b64 and using the resulting mask in s_cbranch_vccnz, without first
ensuring that bits for inactive lanes were clear.
There was already code for inserting an "s_and_b64 vcc, exec, vcc" to
clear bits for inactive lanes in the case that the branch is instruction
selected as s_cbranch_scc1 and is then changed to s_cbranch_vccnz in
SIFixSGPRCopies. I have added the same code into SILowerControlFlow for
the case that the branch is instruction selected as s_cbranch_vccnz.
This de-optimizes the code in some cases where the s_and is not needed,
because vcc is the result of a v_cmp, or multiple v_cmp instructions
combined by s_and/s_or. We should add a pass to re-optimize those cases.
Reviewers: arsenm, kzhuravl
Subscribers: wdng, yaxunl, t-tye, llvm-commits, dstuttard, timcorringham, nhaehnle
Differential Revision: https://reviews.llvm.org/D41292
llvm-svn: 322119
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/uniform-cfg.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/uniform-cfg.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll index a247d7a343f..33a42022705 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-cfg.ll @@ -251,7 +251,7 @@ ENDIF: ; preds = %IF, %main_body ; GCN: s_load_dword [[COND:s[0-9]+]] ; GCN: s_cmp_lt_i32 [[COND]], 1 ; GCN: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]] -; GCN: v_cmp_gt_i32_e64 vcc, [[COND]], 0{{$}} +; GCN: v_cmp_gt_i32_e64 {{[^,]*}}, [[COND]], 0{{$}} ; GCN: s_cbranch_vccz [[BODY:[A-Za-z0-9_]+]] ; GCN: {{^}}[[EXIT]]: ; GCN: s_endpgm |
