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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-08-22 00:50:41 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-08-22 00:50:41 +0000 |
| commit | e8df879948f9da611d88224d87af177ee67be2a7 (patch) | |
| tree | 1119c8924fa76a80f7438c66a461b7445a10b185 /llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll | |
| parent | d6376d987596561c7d34d284f0ec30877b62b311 (diff) | |
| download | bcm5719-llvm-e8df879948f9da611d88224d87af177ee67be2a7.tar.gz bcm5719-llvm-e8df879948f9da611d88224d87af177ee67be2a7.zip | |
AMDGPU: Improve accuracy of instruction rates for some FP instructions
llvm-svn: 245774
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll index 6f608df5e9f..65fe580792a 100644 --- a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll @@ -4,9 +4,9 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone ; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64 ; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} -; SI: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]] -; SI: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32 -; SI: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]] +; SI-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]] +; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]] +; SI-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) { |
