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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-07-14 14:15:03 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-07-14 14:15:03 +0000 |
| commit | e48fe2a27a5cf0f036f8da4dda868fdc2d67f4a2 (patch) | |
| tree | 05621cfebec381c7ed8621cd789a6dbaf0ae4ac7 /llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll | |
| parent | a927a86c72f7715a5a118438eefa442c49c3cff7 (diff) | |
| download | bcm5719-llvm-e48fe2a27a5cf0f036f8da4dda868fdc2d67f4a2.tar.gz bcm5719-llvm-e48fe2a27a5cf0f036f8da4dda868fdc2d67f4a2.zip | |
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
Reviewers: arsenm
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11061
llvm-svn: 242146
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll index dfec8eb15cb..6f608df5e9f 100644 --- a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll @@ -72,11 +72,11 @@ define void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i ; FIXME: select on 0, 0 ; SI-LABEL: {{^}}uint_to_fp_i1_to_f64: -; SI: v_cmp_eq_i32_e64 [[CMP:s\[[0-9]+:[0-9]\]]], -; We can't fold the SGPRs into v_cndmask_b32_e64, because it already -; uses an SGPR for [[CMP]] -; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, v{{[0-9]+}}, [[CMP]] -; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 0, [[CMP]] +; SI: v_cmp_eq_i32_e64 vcc +; We can't fold the SGPRs into v_cndmask_b32_e32, because it already +; uses an SGPR (implicit vcc). +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} +; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 0, vcc ; SI: buffer_store_dwordx2 ; SI: s_endpgm define void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) { |
