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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-14 21:58:07 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-14 21:58:07 +0000 |
| commit | 7900334dd530416b70fb04c8abb6f8c2c65da86d (patch) | |
| tree | 4238b08cd04cf2b886222d38a22d5f543968abf0 /llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll | |
| parent | 34b60f1c405aca79ff0a882f2bebf4128a3f9115 (diff) | |
| download | bcm5719-llvm-7900334dd530416b70fb04c8abb6f8c2c65da86d.tar.gz bcm5719-llvm-7900334dd530416b70fb04c8abb6f8c2c65da86d.zip | |
AMDGPU: Fold bitcasts of scalar constants to vectors
This cleans up some messes since the individual scalar components
can be CSEed.
llvm-svn: 266376
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll index c35f5099fbe..2723c0dc95e 100644 --- a/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll @@ -70,14 +70,13 @@ define void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i ret void } -; FIXME: select on 0, 0 ; SI-LABEL: {{^}}uint_to_fp_i1_to_f64: ; SI: v_cmp_eq_i32_e64 vcc ; We can't fold the SGPRs into v_cndmask_b32_e32, because it already ; uses an SGPR (implicit vcc). -; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} -; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 0, vcc -; SI: buffer_store_dwordx2 +; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}} +; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}} ; SI: s_endpgm define void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) { %cmp = icmp eq i32 %in, 0 |
