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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-22 19:00:09 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-22 19:00:09 +0000 |
| commit | 59bd3014f24004efd3a35132f04e4f82c2d37cec (patch) | |
| tree | 5351c7a26c9b5ce6f2e98a94adced12b3c427fc8 /llvm/test/CodeGen/AMDGPU/texture-input-merge.ll | |
| parent | bb4ff5f5b60a01c51ca9a298307f1f1303c666ab (diff) | |
| download | bcm5719-llvm-59bd3014f24004efd3a35132f04e4f82c2d37cec.tar.gz bcm5719-llvm-59bd3014f24004efd3a35132f04e4f82c2d37cec.zip | |
AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix
These ones aren't directly emitted by mesa and inserted by a pass.
llvm-svn: 258523
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/texture-input-merge.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/texture-input-merge.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/texture-input-merge.ll b/llvm/test/CodeGen/AMDGPU/texture-input-merge.ll index 789538af582..68279f413a1 100644 --- a/llvm/test/CodeGen/AMDGPU/texture-input-merge.ll +++ b/llvm/test/CodeGen/AMDGPU/texture-input-merge.ll @@ -16,16 +16,16 @@ define void @test(<4 x float> inreg %reg0) #0 { %11 = insertelement <4 x float> undef, float %7, i32 0 %12 = insertelement <4 x float> %11, float %5, i32 1 %13 = insertelement <4 x float> undef, float %8, i32 0 - %14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) - %15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) - %16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %14 = call <4 x float> @llvm.r600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %15 = call <4 x float> @llvm.r600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %16 = call <4 x float> @llvm.r600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %17 = fadd <4 x float> %14, %15 %18 = fadd <4 x float> %17, %16 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0) ret void } -declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" }
\ No newline at end of file +attributes #0 = { "ShaderType"="1" } |
