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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-04-30 00:23:06 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-04-30 00:23:06 +0000 |
| commit | cb6ba62d6fce87cc28a5076ccebe05b740d2340d (patch) | |
| tree | a090c0340339618f28dbb530f14c77b5c572588d /llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | |
| parent | 52c68bb0f57fd53e4bd3f721e5fd4ca19544551f (diff) | |
| download | bcm5719-llvm-cb6ba62d6fce87cc28a5076ccebe05b740d2340d.tar.gz bcm5719-llvm-cb6ba62d6fce87cc28a5076ccebe05b740d2340d.zip | |
AMDGPU/SI: Enable the post-ra scheduler
Summary:
This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.
Reviewers: arsenm
Subscribers: qcolombet, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18602
llvm-svn: 268143
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll index 289d6f4eee8..1b386ff7d58 100644 --- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll +++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll @@ -7,9 +7,9 @@ target triple="amdgcn--" ; CHECK: s_load_dword s2, s[0:1], 0x9 ; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb ; CHECK-NEXT: v_mbcnt_lo_u32_b32_e64 +; CHECK-NEXT: v_cmp_eq_i32_e32 vcc, 0, v0 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK: v_cmp_eq_i32_e32 vcc, 0, v0 -; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc +; CHECK: s_and_saveexec_b64 s[2:3], vcc ; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; BB0_1: ; CHECK: s_load_dword s0, s[0:1], 0xa |
