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| author | cdevadas <cdevadas@amd.com> | 2020-01-10 22:23:27 +0530 |
|---|---|---|
| committer | cdevadas <cdevadas@amd.com> | 2020-01-15 15:18:16 +0530 |
| commit | 0dc6c249bffac9f23a605ce4e42a84341da3ddbd (patch) | |
| tree | 113cc776987199087010ef82f8fd4728b06d0c8b /llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | |
| parent | 064859bde79ccd221fd5196fd2d889014c5435c4 (diff) | |
| download | bcm5719-llvm-0dc6c249bffac9f23a605ce4e42a84341da3ddbd.tar.gz bcm5719-llvm-0dc6c249bffac9f23a605ce4e42a84341da3ddbd.zip | |
[AMDGPU] Invert the handling of skip insertion.
The current implementation of skip insertion (SIInsertSkip) makes it a
mandatory pass required for correctness. Initially, the idea was to
have an optional pass. This patch inserts the s_cbranch_execz upfront
during SILowerControlFlow to skip over the sections of code when no
lanes are active. Later, SIRemoveShortExecBranches removes the skips
for short branches, unless there is a sideeffect and the skip branch is
really necessary.
This new pass will replace the handling of skip insertion in the
existing SIInsertSkip Pass.
Differential revision: https://reviews.llvm.org/D68092
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll index 3127201e922..70b7d06e442 100644 --- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll +++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll @@ -18,14 +18,13 @@ define amdgpu_kernel void @foobar(float %a0, float %a1, float addrspace(1)* %out ; CHECK-NEXT: v_mov_b32_e32 v2, s6 ; CHECK-NEXT: v_mov_b32_e32 v3, s7 ; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc -; CHECK-NEXT: ; mask branch BB0_2 -; CHECK-NEXT: BB0_1: ; %ift +; CHECK-NEXT: ; %bb.1: ; %ift ; CHECK-NEXT: s_mov_b32 s4, s5 ; CHECK-NEXT: v_mov_b32_e32 v0, s4 ; CHECK-NEXT: v_mov_b32_e32 v1, s5 ; CHECK-NEXT: v_mov_b32_e32 v2, s6 ; CHECK-NEXT: v_mov_b32_e32 v3, s7 -; CHECK-NEXT: BB0_2: ; %ife +; CHECK-NEXT: ; %bb.2: ; %ife ; CHECK-NEXT: s_or_b64 exec, exec, s[6:7] ; CHECK-NEXT: s_mov_b32 s3, 0xf000 ; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 0 |
