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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-05-09 18:37:39 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-05-09 18:37:39 +0000 |
| commit | 762d49880876eca14aa75a1bc893eba23ed50788 (patch) | |
| tree | 2d8e059a73d5b7c2f2e60458e71e2503e58dadad /llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll | |
| parent | 73634e40378fdba2b39c777a871961af2651b4e0 (diff) | |
| download | bcm5719-llvm-762d49880876eca14aa75a1bc893eba23ed50788.tar.gz bcm5719-llvm-762d49880876eca14aa75a1bc893eba23ed50788.zip | |
AMDGPU: Add combine for trunc of bitcast from build_vector
If the truncate is only accessing the first element of the vector,
we can use the original source value.
This helps with some combine ordering issues after operations are
lowered to integer operations between bitcasts of build_vector.
In particular it stops unnecessarily materializing the unused
top half of a vector in some cases.
llvm-svn: 331909
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll index fd82dccb0fa..280ce628c18 100644 --- a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll +++ b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll @@ -3,18 +3,28 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; GCN-LABEL: {{^}}local_store_i56: -; GCN-DAG: ds_write_b8 v0, v{{[0-9]+}} offset:6 -; GCN-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4 -; GCN-DAG: ds_write_b32 v0, v{{[0-9]+$}} +; CIVI-DAG: ds_write_b8 v0, v{{[0-9]+}} offset:6 +; CIVI-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4 +; CIVI-DAG: ds_write_b32 v0, v{{[0-9]+$}} + +; GFX9-DAG: ds_write_b8_d16_hi v0, v{{[0-9]+}} offset:6 +; GFX9-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4 +; GFX9-DAG: ds_write_b32 v0, v{{[0-9]+$}} + + define void @local_store_i56(i56 addrspace(3)* %ptr, i56 %arg) #0 { store i56 %arg, i56 addrspace(3)* %ptr, align 8 ret void } ; GCN-LABEL: {{^}}local_store_i55: -; GCN-DAG: ds_write_b8 v0, v{{[0-9]+}} offset:6 -; GCN-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4 -; GCN-DAG: ds_write_b32 v0, v{{[0-9]+$}} +; CIVI-DAG: ds_write_b8 v0, v{{[0-9]+}} offset:6 +; CIVI-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4 +; CIVI-DAG: ds_write_b32 v0, v{{[0-9]+$}} + +; GFX9-DAG: ds_write_b8_d16_hi v0, v{{[0-9]+}} offset:6 +; GFX9-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4 +; GFX9-DAG: ds_write_b32 v0, v{{[0-9]+$}} define amdgpu_kernel void @local_store_i55(i55 addrspace(3)* %ptr, i55 %arg) #0 { store i55 %arg, i55 addrspace(3)* %ptr, align 8 ret void |
