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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-11 06:02:01 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-11 06:02:01 +0000 |
| commit | 9c47dd583a94f457411df5403eff4228cc3690cd (patch) | |
| tree | bf0d49daf75b9ec932dc33135e9c6c8c193d9f3c /llvm/test/CodeGen/AMDGPU/store-barrier.ll | |
| parent | 4244be25bd7c438ac755813ff33e6e80ca6b6f34 (diff) | |
| download | bcm5719-llvm-9c47dd583a94f457411df5403eff4228cc3690cd.tar.gz bcm5719-llvm-9c47dd583a94f457411df5403eff4228cc3690cd.zip | |
AMDGPU: Remove some old intrinsic uses from tests
llvm-svn: 260493
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/store-barrier.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/store-barrier.ll | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/store-barrier.ll b/llvm/test/CodeGen/AMDGPU/store-barrier.ll index ba4049f28a6..58ff069133a 100644 --- a/llvm/test/CodeGen/AMDGPU/store-barrier.ll +++ b/llvm/test/CodeGen/AMDGPU/store-barrier.ll @@ -12,7 +12,7 @@ ; CHECK: s_barrier ; CHECK: s_endpgm ; Function Attrs: nounwind -define void @test(<2 x i8> addrspace(3)* nocapture %arg, <2 x i8> addrspace(1)* nocapture readonly %arg1, i32 addrspace(1)* nocapture readonly %arg2, <2 x i8> addrspace(1)* nocapture %arg3, i32 %arg4, i64 %tmp9) { +define void @test(<2 x i8> addrspace(3)* nocapture %arg, <2 x i8> addrspace(1)* nocapture readonly %arg1, i32 addrspace(1)* nocapture readonly %arg2, <2 x i8> addrspace(1)* nocapture %arg3, i32 %arg4, i64 %tmp9) #0 { bb: %tmp10 = getelementptr inbounds i32, i32 addrspace(1)* %arg2, i64 %tmp9 %tmp13 = load i32, i32 addrspace(1)* %tmp10, align 2 @@ -21,7 +21,7 @@ bb: %tmp16 = add i32 %tmp13, 1 %tmp17 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp16 store <2 x i8> %tmp15, <2 x i8> addrspace(3)* %tmp17, align 2 - tail call void @llvm.AMDGPU.barrier.local() #2 + tail call void @llvm.amdgcn.s.barrier() %tmp25 = load i32, i32 addrspace(1)* %tmp10, align 4 %tmp26 = sext i32 %tmp25 to i64 %tmp27 = sext i32 %arg4 to i64 @@ -37,6 +37,7 @@ bb: } ; Function Attrs: convergent nounwind -declare void @llvm.AMDGPU.barrier.local() #2 +declare void @llvm.amdgcn.s.barrier() #1 -attributes #2 = { convergent nounwind } +attributes #0 = { nounwind } +attributes #1 = { convergent nounwind } |
