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authorGuozhi Wei <carrot@google.com>2019-01-25 19:45:13 +0000
committerGuozhi Wei <carrot@google.com>2019-01-25 19:45:13 +0000
commit81f3fd4bf81247480d2fa172a65b04951e7a0d3e (patch)
tree0bb6b2d6785872d844ecf88b1a11a1001f54d6cb /llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
parent165ea58798b2f51180a44ae734d8da8a06abf81a (diff)
downloadbcm5719-llvm-81f3fd4bf81247480d2fa172a65b04951e7a0d3e.tar.gz
bcm5719-llvm-81f3fd4bf81247480d2fa172a65b04951e7a0d3e.zip
[MBP] Don't move bottom block before header if it can't reduce taken branches
If bottom of block BB has only one successor OldTop, in most cases it is profitable to move it before OldTop, except the following case: -->OldTop<- | . | | . | | . | ---Pred | | | BB----- Move BB before OldTop can't reduce the number of taken branches, this patch detects this case and prevent the moving. Differential Revision: https://reviews.llvm.org/D57067 llvm-svn: 352236
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll')
-rw-r--r--llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll18
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
index 6215a486a36..ad68d300de0 100644
--- a/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
@@ -96,20 +96,20 @@ declare float @llvm.fabs.f32(float) nounwind readnone
; FUNC-LABEL: {{^}}loop_land_info_assert:
; SI: v_cmp_lt_i32_e64 [[CMP4:s\[[0-9:]+\]]], s{{[0-9]+}}, 4{{$}}
; SI: s_and_b64 [[CMP4M:s\[[0-9]+:[0-9]+\]]], exec, [[CMP4]]
-; SI: s_mov_b64 vcc, [[CMP4M]]
-; SI-NEXT: s_cbranch_vccnz [[CONVEX_EXIT:BB[0-9_]+]]
-; SI-NEXT: s_branch [[FOR_COND_PREHDR:BB[0-9_]+]]
+; SI: s_branch [[INFLOOP:BB[0-9]+_[0-9]+]]
+
+; SI: [[CONVEX_EXIT:BB[0-9_]+]]
+; SI: s_mov_b64 vcc,
+; SI-NEXT: s_cbranch_vccnz [[ENDPGM:BB[0-9]+_[0-9]+]]
+; SI: s_cbranch_vccnz [[INFLOOP]]
; SI: ; %if.else
; SI: buffer_store_dword
-; SI: [[INFLOOP:BB[0-9]+_[0-9]+]]:
+; SI: [[INFLOOP]]:
+; SI: s_cbranch_vccnz [[CONVEX_EXIT]]
-; SI: [[CONVEX_EXIT]]:
-; SI: s_mov_b64 vcc,
-; SI-NEXT: s_cbranch_vccnz [[ENDPGM:BB[0-9]+_[0-9]+]]
-; SI: s_branch [[INFLOOP]]
-; SI-NEXT: [[FOR_COND_PREHDR]]:
+; SI: ; %for.cond.preheader
; SI: s_cbranch_vccz [[ENDPGM]]
; SI: [[ENDPGM]]:
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