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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-09-09 15:43:26 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-09-09 15:43:26 +0000 |
| commit | 9a197676b13333be2d4628a413e863ce44ab6697 (patch) | |
| tree | e0cec7b57d87246eac7d90b5e216b5aae8997a6e /llvm/test/CodeGen/AMDGPU/select64.ll | |
| parent | a3e27edb5d2cc6c4c5ec85ce8de19b3177c07bd0 (diff) | |
| download | bcm5719-llvm-9a197676b13333be2d4628a413e863ce44ab6697.tar.gz bcm5719-llvm-9a197676b13333be2d4628a413e863ce44ab6697.zip | |
AMDGPU/SI: Fold operands through REG_SEQUENCE instructions
Summary:
This helps mostly when we use add instructions for address calculations
that contain immediates.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D12256
llvm-svn: 247157
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/select64.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/select64.ll | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/select64.ll b/llvm/test/CodeGen/AMDGPU/select64.ll index 13fb575b2b1..a68fdecb00a 100644 --- a/llvm/test/CodeGen/AMDGPU/select64.ll +++ b/llvm/test/CodeGen/AMDGPU/select64.ll @@ -51,12 +51,8 @@ define void @v_select_trunc_i64_2(i32 addrspace(1)* %out, i32 %cond, i64 addrspa } ; CHECK-LABEL: {{^}}v_select_i64_split_imm: -; CHECK: s_mov_b32 [[SHI:s[0-9]+]], 63 -; CHECK: s_mov_b32 [[SLO:s[0-9]+]], 0 -; CHECK-DAG: v_mov_b32_e32 [[VHI:v[0-9]+]], [[SHI]] -; CHECK-DAG: v_mov_b32_e32 [[VLO:v[0-9]+]], [[SLO]] -; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, [[VLO]], {{v[0-9]+}} -; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, [[VHI]], {{v[0-9]+}} +; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}} +; CHECK-DAG: v_cndmask_b32_e32 {{v[0-9]+}}, 63, {{v[0-9]+}} ; CHECK: s_endpgm define void @v_select_i64_split_imm(i64 addrspace(1)* %out, i32 %cond, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %cmp = icmp ugt i32 %cond, 5 |
