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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-16 20:35:23 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-16 20:35:23 +0000 |
| commit | 3b36bb1d8780caeb122ee86cf2f44e397cb028ea (patch) | |
| tree | 8bfac477c9af17ec001ff7b7f479d6cd7dd5e91f /llvm/test/CodeGen/AMDGPU/select-vectors.ll | |
| parent | 1b9560ffd61f3f4c2089c4971ebce0cfb4932adf (diff) | |
| download | bcm5719-llvm-3b36bb1d8780caeb122ee86cf2f44e397cb028ea.tar.gz bcm5719-llvm-3b36bb1d8780caeb122ee86cf2f44e397cb028ea.zip | |
AMDGPU: Enable ConstrainCopy DAG mutation
This fixes a probably unintended divergence from the default
scheduler behavior.
llvm-svn: 287146
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/select-vectors.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/select-vectors.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/select-vectors.ll b/llvm/test/CodeGen/AMDGPU/select-vectors.ll index 240235138c8..fa617fd09fc 100644 --- a/llvm/test/CodeGen/AMDGPU/select-vectors.ll +++ b/llvm/test/CodeGen/AMDGPU/select-vectors.ll @@ -93,13 +93,13 @@ define void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> ; SI-DAG: s_load_dwordx2 s{{\[}}[[ALO:[0-9]+]]:[[AHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; SI-DAG: s_load_dwordx2 s{{\[}}[[BLO:[0-9]+]]:[[BHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} -; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]] -; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]] ; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]] +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]] +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]] ; SI-DAG: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]] ; SI: v_cndmask_b32_e32 -; SI: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]] ; SI: v_cndmask_b32_e32 ; SI: buffer_store_dwordx2 define void @s_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind { |
