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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-01-12 18:58:15 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-01-12 18:58:15 +0000
commit45337df08f99529e1543ecb7c236ea63707c673b (patch)
tree3b19ee9af4f7f87b8cf9edb2babb3c50768b9fd4 /llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
parentc4427a39760a45e3fd16e403ecfa81c84114a499 (diff)
downloadbcm5719-llvm-45337df08f99529e1543ecb7c236ea63707c673b.tar.gz
bcm5719-llvm-45337df08f99529e1543ecb7c236ea63707c673b.zip
AMDGPU: Skip fneg/select combine if it can fold into other
llvm-svn: 291792
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll')
-rw-r--r--llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll46
1 files changed, 46 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
new file mode 100644
index 00000000000..559d464f36a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract-legacy.ll
@@ -0,0 +1,46 @@
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+
+; --------------------------------------------------------------------------------
+; Don't fold if fneg can fold into the source
+; --------------------------------------------------------------------------------
+
+; GCN-LABEL: {{^}}select_fneg_posk_src_rcp_legacy_f32:
+; GCN: buffer_load_dword [[X:v[0-9]+]]
+
+; GCN: v_rcp_legacy_f32_e32 [[RCP:v[0-9]+]], [[X]]
+; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[RCP]], vcc
+; GCN: v_xor_b32_e32 [[NEG_SELECT:v[0-9]+]], 0x80000000, [[SELECT]]
+; GCN-NEXT: buffer_store_dword [[NEG_SELECT]]
+define void @select_fneg_posk_src_rcp_legacy_f32(i32 %c) #2 {
+ %x = load volatile float, float addrspace(1)* undef
+ %y = load volatile float, float addrspace(1)* undef
+ %cmp = icmp eq i32 %c, 0
+ %rcp = call float @llvm.amdgcn.rcp.legacy(float %x)
+ %fneg = fsub float -0.0, %rcp
+ %select = select i1 %cmp, float %fneg, float 2.0
+ store volatile float %select, float addrspace(1)* undef
+ ret void
+}
+
+; GCN-LABEL: {{^}}select_fneg_posk_src_mul_legacy_f32:
+; GCN: buffer_load_dword [[X:v[0-9]+]]
+
+; GCN: v_mul_legacy_f32_e32 [[MUL:v[0-9]+]], 4.0, [[X]]
+; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[MUL]], vcc
+; GCN: v_xor_b32_e32 [[NEG_SELECT:v[0-9]+]], 0x80000000, [[SELECT]]
+; GCN-NEXT: buffer_store_dword [[NEG_SELECT]]
+define void @select_fneg_posk_src_mul_legacy_f32(i32 %c) #2 {
+ %x = load volatile float, float addrspace(1)* undef
+ %cmp = icmp eq i32 %c, 0
+ %mul = call float @llvm.amdgcn.fmul.legacy(float %x, float 4.0)
+ %fneg = fsub float -0.0, %mul
+ %select = select i1 %cmp, float %fneg, float 2.0
+ store volatile float %select, float addrspace(1)* undef
+ ret void
+}
+
+declare float @llvm.amdgcn.rcp.legacy(float) #1
+declare float @llvm.amdgcn.fmul.legacy(float, float) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
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