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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-17 22:47:26 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-17 22:47:26 +0000 |
| commit | 456b93b4c2af5aaa855bf2993d1a37a4c062a966 (patch) | |
| tree | 276034e683b06fceb2b1b3dd8dc06ef5e073790d /llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll | |
| parent | 320b9ca2589e8cd433c6c74967c38005262bda43 (diff) | |
| download | bcm5719-llvm-456b93b4c2af5aaa855bf2993d1a37a4c062a966.tar.gz bcm5719-llvm-456b93b4c2af5aaa855bf2993d1a37a4c062a966.zip | |
AMDGPU: Convert tests away from llvm.SI.load.const
llvm-svn: 351494
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll b/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll index d93cde6a885..be76371c42d 100644 --- a/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll @@ -15,9 +15,9 @@ target triple = "amdgcn--" define amdgpu_gs void @main(i32 inreg %arg) #0 { main_body: - %tmp = call float @llvm.SI.load.const.v4i32(<4 x i32> undef, i32 20) - %tmp1 = call float @llvm.SI.load.const.v4i32(<4 x i32> undef, i32 24) - %tmp2 = call float @llvm.SI.load.const.v4i32(<4 x i32> undef, i32 48) + %tmp = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 20, i32 0) + %tmp1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 24, i32 0) + %tmp2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 48, i32 0) %array_vector3 = insertelement <4 x float> zeroinitializer, float %tmp2, i32 3 %array_vector5 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %tmp, i32 1 %array_vector6 = insertelement <4 x float> %array_vector5, float undef, i32 2 @@ -45,7 +45,7 @@ main_body: ret void } -declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1 +declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1 declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #2 declare void @llvm.amdgcn.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #3 |
