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| author | Scott Linder <scott@scottlinder.com> | 2018-10-31 18:54:06 +0000 |
|---|---|---|
| committer | Scott Linder <scott@scottlinder.com> | 2018-10-31 18:54:06 +0000 |
| commit | c6c627253db6b273dd995771e7af17c53858eaba (patch) | |
| tree | 0bf7409b44ebdf69c4d2d6b4972514ac0ecef5d9 /llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll | |
| parent | 7c7cac05ed936fad0cefc888d2f30ceb47291ff5 (diff) | |
| download | bcm5719-llvm-c6c627253db6b273dd995771e7af17c53858eaba.tar.gz bcm5719-llvm-c6c627253db6b273dd995771e7af17c53858eaba.zip | |
[AMDGPU] Remove FeatureVGPRSpilling
This feature is only relevant to shaders, and is no longer used. When disabled,
lowering of reserved registers for shaders causes a compiler crash.
Remove the feature and add a test for compilation of shaders at OptNone.
Differential Revision: https://reviews.llvm.org/D53829
llvm-svn: 345763
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll b/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll index ff3d0fc9bfa..96ebb6f8362 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll +++ b/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -march=amdgcn -verify-machineinstrs -mattr=+vgpr-spilling < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+vgpr-spilling < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s declare void @llvm.amdgcn.s.barrier() nounwind convergent |
