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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-05-02 17:39:06 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-05-02 17:39:06 +0000 |
| commit | 1f520e5c98a0fbeaa1347ea1e58a3f58721ae98c (patch) | |
| tree | 8b8ede37f32568e74beb048b09157f87bef3c498 /llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll | |
| parent | 119d3d80cbb53ff601f5bf56affb464d3b5f55ea (diff) | |
| download | bcm5719-llvm-1f520e5c98a0fbeaa1347ea1e58a3f58721ae98c.tar.gz bcm5719-llvm-1f520e5c98a0fbeaa1347ea1e58a3f58721ae98c.zip | |
AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses
Summary:
Add support for detecting hazards in SMEM soft clauses, so that we only
break the clauses when necessary, either by adding s_nop or re-ordering
other alu instructions.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18870
llvm-svn: 268260
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll b/llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll index f5cfd23e873..ade9e775d9d 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll +++ b/llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll @@ -2,18 +2,15 @@ ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=VI --check-prefix=GCN %s ; FUNC-LABEL: {{^}}cluster_arg_loads: -; FIXME: Due to changes in the load clustering heuristics. We now longer -; cluster all argument loads together. +; FIXME: Due to changes in the load clustering heuristics. We no longer +; cluster all argument loads together on SI. ; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd ; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xe ; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9 ; SI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 -; VI-NEXT: s_nop 0 ; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x38 -; VI-NEXT: s_nop 0 -; VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x24 -; VI-NEXT: s_nop 0 +; VI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x24 ; VI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c define void @cluster_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %x, i32 %y) nounwind { store i32 %x, i32 addrspace(1)* %out0, align 4 |
