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authorMatthias Braun <matze@braunis.de>2016-06-24 23:52:11 +0000
committerMatthias Braun <matze@braunis.de>2016-06-24 23:52:11 +0000
commit1e374a7aa67165180c45bb08fc156f3d64e272af (patch)
treede31648d168dfca6dad89a67e181d5da1dff5beb /llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
parentd7f71add86c892ced324fc26cb0945911f3e26a5 (diff)
downloadbcm5719-llvm-1e374a7aa67165180c45bb08fc156f3d64e272af.tar.gz
bcm5719-llvm-1e374a7aa67165180c45bb08fc156f3d64e272af.zip
AMDGPU: Define a schedule class for COPY.
COPY was lacking a scheduling class, define it to avoid regressions in the upcoming change to the bidirectional MachineScheduler. Approved by tstellar on IRC. Differential Revision: http://reviews.llvm.org/D21540 llvm-svn: 273751
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll')
-rw-r--r--llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll b/llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
index fb33be800dd..886d4a1dcb5 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll
@@ -5,13 +5,13 @@
; FIXME: Due to changes in the load clustering heuristics. We no longer
; cluster all argument loads together on SI.
; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
-; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xe
; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9
; SI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
+; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xe
; VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
-; VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x38
; VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x24
; VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x38
define void @cluster_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %x, i32 %y) nounwind {
store i32 %x, i32 addrspace(1)* %out0, align 4
store i32 %y, i32 addrspace(1)* %out1, align 4
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