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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-27 22:15:25 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-27 22:15:25 +0000 |
| commit | eb522e68bc8ee92d9ee38aced7719e3a1789b631 (patch) | |
| tree | 226c01daee0eb90653e5f9e807bb39f044fd0ebf /llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | |
| parent | b2605f31ed27aceefbb135c3fb3178687f07741c (diff) | |
| download | bcm5719-llvm-eb522e68bc8ee92d9ee38aced7719e3a1789b631.tar.gz bcm5719-llvm-eb522e68bc8ee92d9ee38aced7719e3a1789b631.zip | |
AMDGPU: Support v2i16/v2f16 packed operations
llvm-svn: 296396
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll index f8f21af5bda..35886f85618 100644 --- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll +++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll @@ -67,10 +67,9 @@ define void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspac ; ret void ; } -; define void @scalar_to_vector_test6(<4 x i16> addrspace(1)* %out) nounwind { -; %newvec0 = insertelement <2 x i32> undef, i32 12345, i32 0 -; %bc = bitcast <2 x i32> %newvec0 to <4 x i16> -; %add = add <4 x i16> %bc, <i16 1, i16 2, i16 3, i16 4> -; store <4 x i16> %add, <4 x i16> addrspace(1)* %out, align 16 -; ret void -; } +define void @scalar_to_vector_test6(<2 x half> addrspace(1)* %out, i8 zeroext %val) nounwind { + %newvec0 = insertelement <4 x i8> undef, i8 %val, i32 0 + %bc = bitcast <4 x i8> %newvec0 to <2 x half> + store <2 x half> %bc, <2 x half> addrspace(1)* %out + ret void +} |
